Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

2001-11-15

2003-04-08

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S203000

Reexamination Certificate

active

06545902

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a ferroelectric memory device. And more particularly, the invention relates to a ferroelectric memory device having memory cells each of which is made up of a capacitor with an insulating film of ferroelectric material and a MOS transistor.
BACKGROUND ART
As a nonvolatile memory realizing high-speed write operation, much attention has been recently focused on a ferroelectric memory which uses a ferroelectric capacitor. In particular, a memory of such a type that each memory cell is made up of a capacitor with an insulating film of ferroelectric material and a MOS transistor and a constant voltage is applied to one of electrodes of the capacitor called a plate has a possibility of being able to realize a nonvolatile memory with nearly the same operating speed and area as those of a dynamic random access memory (DRAM). An example of a basic arrangement of such a prior art ferroelectric memory is shown in FIG.
36
. In the drawing, reference symbol MC denotes a memory cell, which is made up of a ferroelectric capacitor with an insulating film of ferroelectric material such as PZT and an NMOS transistor. The remanent polarization of the ferroelectric capacitor stores information. The ferroelectric capacitor is connected at its one end to the NMOS transistor and at the other end (plage electrode) to ½ voltage (VCC/2) corresponding to half of a source voltage VCC. For simplicity, only one memory cell MC is illustrated in the illustrated example, but actually a plurality of such memory cells are connected to each of a pair Dt and Db of data lines and are selected by a word line W for data transfer to the data-line pair Dt or Db. Although omitted for simplicity in the drawing, a dummy cell is actually provided to each of the data-line pair Dt and Db. Reference symbol PC denotes a precharge circuit which precharges the data-line pair Dt and Db to a ground voltage VSS. Reference symbol SA denotes a sense amplifier which detects voltages of the data-line pair Dt and Db and amplifies the voltages differentially. Further, though omitted for simplicity in the drawing, a switch is actually provided to the sense amplifier for signal transfer to or from external.
The operation of the above arrangement will be explained with use of a timing chart shown in FIG.
37
. In a standby state, a control signal FPC causes the precharge circuit PC to be put in its ON state, so that the data-line pair Dt and Db are precharged to the ground voltage VSS, that is, are in a so-called VSS precharge state. In operation, the control signal FPC causes the precharge circuit PC to be turned OFF. Thus when the word line W has a selected-word-line voltage VCH, the memory cell MC is selected. This causes an NMOS transistor in the memory cell MC to be turned ON, so that a voltage of VCC/2 corresponding to a difference in voltage between a data line Dt and a plate electrode is applied to the ferroelectric capacitor, whereby the remanent polarization is read out as charge to the data line Dt. This varies the voltage on the data line Dt and then a control signal FSA activates the sense amplifier SA, which in turn amplifies the voltage of the data line D with positive feedback to sense data. Though not illustrated in
FIG. 37
, when the data sensed by the sense amplifier SA is output externally, read operation is carried out. Further, when the voltage of the data line is used as a write voltage in accordance with externally entered data, write operation is carried out. When the word line W is lowered to turn OFF the NMOS transistor in the memory cell MC, rewrite operation to the memory cell MC is carried out. Thereafter, the control signal FSA stops the operation of the sense amplifier SA, the control signal FPC turns ON a precharging switch, thus returning the current state to the standby mode.
The operation of the ferroelectric capacitor in the standby mode will be explained with use of a hysteresis characteristic shown in FIG.
38
. In the drawing, horizontal axis denotes a voltage applied to the ferroelectric capacitor with the voltage of the plate electrode as a reference, and vertical axis denotes a charge amount stored in the ferroelectric capacitor including polarization. In such a condition that no voltage is applied to the ferroelectric capacitor in the standby state, the ferroelectric capacitor retains remanent polarization and takes a position of either point PS
0
or PS
1
in
FIG. 38
depending on data “0” or “1” stored in the capacitor. When it is desired to read out a signal from the memory cell MC to the data line D, the data line D is precharged to −VCC/2 with the voltage of the plate electrode as a reference, so that a data-line capacitance CD is represented by load lines LL
0
and LL
1
having a gradient of −CD in FIG.
38
. Intersections of the load lines and hysteresis characteristics are points which the ferroelectric capacitor takes in its read mode. Meanwhile, the write operation is carried out when the capacitors takes a point PW
0
or PW
1
in
FIG. 38
with the data line D having the voltage of VSS or VCC.
As has been explained above, in the ferroelectric memory device, the voltage is applied to the ferroelectric capacitor to cause the reverse polarization to generate charge on the data line.
The following schemes which relate to the present application and are directed to DRAMs have been disclosed.
Disclosed in JP-A-62-180591 is a scheme of dividing a precharge voltage of a data-line pair into two in order to reduce array noise.
Also disclosed in JP-A-5-135580 is a scheme of transferring charge between sense amplification groups in order to reduce a charge amount consumed in rewrite and precharge operation.
Further disclosed in JP-A-4-184787 is a scheme of dividing a precharge voltage of a data-line pair in a memory cell array into two to transfer charge between two data-line pairs. The present application will be explained in association with these schemes.
DISCLOSURE OF INVENTION
In a ferroelectric memory device, in order to generate a signal voltage on a data line, a voltage must be applied to a ferroelectric capacitor. Thus, when a plate is set to have a constant voltage, it is impossible to employ the scheme which reads out a signal with the data line precharged to VCC/2 and is widely used in DRAM fields, that is, a so-called VCC/2 precharge scheme. And the ferroelectric memory device has drawbacks including the three problems discussed below, when compared to a DRAM of the above VCC/2 precharge scheme.
First, the device has a large array noise. More specifically, a ferroelectric memory employs a VSS precharge scheme (or VCC precharge scheme). Thus a signal is read-out from one memory cell in all data lines, the voltage varies from VSS toward a higher level (from VCC toward a lower level in the VCC precharge scheme). For this reason, large coupling noise takes place in non-selected word lines or wells coupled capacitively with them. The noise is again capacitively coupled with the data lines to fluctuate the voltages of the data lines. Meanwhile, when a voltage at a storage-node in a selected memory cell drops, a plate voltage is lowered through a ferroelectric capacitor. This voltage applied to the ferroelectric capacitor in the memory cell becomes small, so that a part of the remanent polarization of ferroelectric material to be read out as charge becomes small in amount, thus decreasing an S/N ratio. In the VSS precharge scheme, when a voltage between the data-line pair is amplified by a sense amplifier, one of the voltages of the data lines in the pair is charged to VCC by the sense amplifier with a large variation, whereas the other voltage is discharged to VSS with a small variation. For this reason, great coupling noise takes place in all nodes capacitively coupled with the data-line pair, increasing the voltage. The noise is again capacitively coupled with the data lines so that differences in the magnitude of coupling capacitance between the data line pairs result in differential noise, thus reducing the S/N rati

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