Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

2001-09-07

2002-12-10

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S210130, C365S200000

Reexamination Certificate

active

06493251

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2000-274222, filed on Sep. 8, 2000, the contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to ferroelectric memory devices for storing data in a nonvolatile manner by the use of ferroelectric capacitors, and, more particularly, to a ferroelectric memory device having a cell block formed of series-connected plural unit cells each including a parallel-connected ferroelectric capacitor and a memory cell transistor.
2. Description of Related Art
A ferroelectric memory device stores binary data in a nonvolatile manner in accordance with the value of remanent polarization of a ferroelectric capacitor. Generally, a memory cell of a conventional ferroelectric memory device is formed by series-connecting a ferroelectric capacitor and a transistor, as in the case of a DRAM. However, unlike a DRAM, a ferroelectric memory device stores data by remanent polarization. Accordingly, it is necessary to drive a plate line in order to read out a signal charge to a bit line. Therefore, a ferroelectric memory device requires a plate line driving circuit for driving a plate line. However, in a conventional ferroelectric memory device, a plate line driving circuit takes up significant space.
A cell array arrangement of a ferroelectric memory device, in which the area of a plate line driving circuit can be reduced, has been proposed by Takashima et al. In this arrangement, both sides of a ferroelectric capacitor (C) are connected to a source and a drain of a cell transistor (T) to form a unit cell, and a plurality of such unit cells are series-connected to form a cell block (D. Takashima et al., “High-density chain ferroelectric random memory (CFeRAM)” in Proc. VSLI Symp. June 1997, pp. 83-84). In this series connected TC unit type ferroelectric memory device, a plate line driving circuit can be shared by, e.g., eight unit cells. Therefore, a cell array can be highly integrated.
FIG. 24
shows a configuration of a memory cell array
1
of such a series connected TC unit type ferroelectric memory device. A unit cell MC consists of parallel-connected ferroelectric capacitor C and cell transistor T. In the example of
FIG. 24
, eight of such unit cells are series-connected to form a cell block MCB.
FIG. 24
shows two cell blocks MCB
0
and MCB
1
connected to a pair of bit lines BBL and BL, respectively.
One end of the cell block MCB
0
is connected to the bit line BBL via a block selecting transistor BST
0
and one end of the cell block MCB
1
is connected to the bit line BL via a block selecting transistor BST
1
. The other end of the cell block MCB
0
is connected to a plate line BPL, and the other end of the cell block MCB
1
is connected to a plate line PL. Gates of cell transistors in each cell block are connected to word lines WL
0
-WL
7
. A sense amplifier SA for sensing and amplifying read data is connected to the bit lines BL and BBL. Block selecting signals BS
0
and BS
1
are inputted to gates of the block selecting transistors BST
0
and BST
1
, respectively.
FIG. 25
is a timing chart showing basic operations of such a ferroelectric memory device. In this case, a unit cell stores data as data “1” when the remanent polarization of the ferroelectric capacitor is in a positive state, and store data as data “0” when the remanent polarization of the ferroelectric capacitor is in a negative state. In a standby mode, all the word lines are held to be at “H”, the block selecting signals BS
0
, BS
1
are held to be at “L”, and the bit lines BL, BBL and the plate lines PL, BPL are held to be at VSS (ground potential). At this time, the terminals of the ferroelectric capacitors C are shunted by the ON-state cell transistors so as to store data stably.
In an active mode, when a unit cell at the side of the bit line BL is selected by, e.g., the word line WL
2
, the bit line BL is held to be in a floating state to set the word line WL
2
to be at “L”, and then, the block selecting signal BS
1
is held to be at “H”, and the electric potential of the plate line PL is raised from VSS (ground potential) to VAA (positive potential). In this way, a voltage is applied to the ferroelectric capacitor of the selected unit cell, and a voltage signal is read to the bit line BL in accordance with whether the data is data “0” or data “1”.
The voltage signal read to the bit line BL is detected as a result of a comparison with a reference voltage Vref applied to the bit line BBL, which is paired with the bit line BL. That is, when a sense amplifier activating signal SE is raised, the sense amplifier SA sets the bit line BL to be at VAA if the data “1” is read, and at VSS if the data “0” is read. After that, by deactivating the sense amplifier SA, the read data is rewritten.
In these reading and rewriting operations, when the data “1” is read, a destructive read is performed, and when the data “0” is read, a nondestructive read is performed. That is, when the data “1” is read, the remanent polarization of the ferroelectric capacitor is remarkably reduced due to the addition of a positive voltage from the plate line PL, thereby causing a polarization reversal. After the reading operation, when the voltage of the plate line is lowered, since the bit line is held to be at a high potential by the read data, a reverse voltage of the voltage at the time of the reading operation is applied to the ferroelectric capacitor to perform the rewriting operation until the remanent polarization reaches the +Pr again. When the data “0” is read, no polarization reversal is caused by the plate line voltage. Further, no reversal voltage is applied after the reading operation. Therefore, the rewriting operation is performed while the remanent polarization remains negative.
In the above-described operations, the value of the read signal is determined by the capacitance of the bit line and the characteristic curves of the ferroelectric capacitor.
FIG. 26
shows the relationship between the characteristic curves (hysteresis loop) and the value of the read signal. The positive voltage VAA supplied from the plate line side to the ferroelectric capacitor is shown as −VAA on the minus voltage axis, and the positive voltage VAA supplied from the bit line side to the ferroelectric capacitor is shown as VAA on the plus voltage axis. The bit line capacitance is shown as Cb. As shown in
FIG. 26
, the risings in potential of the bit line at the time of reading “1” data and “0” data can be obtained as the intersections of load lines having the inclination of −Cb and the hysteresis loop. In this case, the risings in voltage of the bit line are shown relative to −VAA.
As is apparent from
FIG. 26
, the read potentials of the “1” data and “0” data are lowered as the bit line capacitance Cb increases. Therefore, the read signal value, which is the difference between these potentials, also depends on the bit line capacitance Cb. Unlike a typical DRAM, the bit line capacitance dependency of the read signal value reaches the maximum value at a certain value of the bit line capacitance.
A series connected TC unit type ferroelectric memory device has a characteristic that the bit line load capacitance Cb differs depending on the position of the selected word line in the cell block. That is, if the case where a memory cell most distant from the bit line is selected by the word line WL
7
is compared with the case where a memory cell closest to the bit line is selected by the word line WL
0
, the bit line capacitance is greater in the former case since the parasitic capacitances of the unit cells connected to the word lines WL
0
-WL
6
are added as loads.
FIG. 27
shows that the bit line capacitance Cb substantially changes in accordance with the position of the selected word line, thereby changing the read signal value. The read signal potential is lower in the case of selecting the word line WL
7
than the case o

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