Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

2000-09-13

2002-03-05

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S203000, C365S189011

Reexamination Certificate

active

06353550

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory device including memory cells each having a ferroelectric capacitor.
With the recent widespread use of small, high-performance electronic equipment provided with memory function, such as portable terminals and IC cards, demands for nonvolatile memories with low voltage, low power consumption, and high-speed operation suitable for such electronic equipment have increased. Flush memories are typical of non-volatile memories. From the standpoint of low power consumption and high-speed operation, however, ferroelectric memories have attracted attention. A ferroelectric memory stores non-volatile data utilizing the difference in the polarizing direction of a capacitor having a ferroelectric film. Accordingly, to rewrite data, only required is applying an electric field for inverting the polarizing direction. This has therefore features of low voltage, low power consumption, and high-speed operation.
A conventional configuration of memory cells constituting such a ferroelectric memory will be described with reference to
FIGS. 21 through 23
.
FIG. 21
is an electric circuit diagram of a memory cell array of a conventional ferroelectric memory.
As shown in
FIG. 21
, the memory cell array of the conventional ferroelectric memory includes: a number of bit lines BL and a number of word lines WL extending to cross with each other; and a number of memory cells arranged in a matrix at positions corresponding to the respective crossings of the lines. Each memory cell includes: one memory cell transistor Q the gate electrode of which receives a signal from the word line WL; and one ferroelectric capacitor C interposed between the source region of the memory cell transistor Q and a cell plate line PL.
FIG. 21
only illustrates four word lines WLa to WLd, four cell plate lines PLa to PLd, four bit lines BLa to BLd, and 16 sets of memory cell transistors Qaa to Qdd, and ferroelectric capacitors Caa to Cdd. It should be understood that the numbers of word lines and the like corresponding to the memory capacity (number of bits) of the ferroelectric memory are actually arranged. This also applies to
FIGS. 22 and 23
to be described later.
The ferroelectric capacitor C includes a first electrode connected to the source region of the memory cell transistor and a second electrode connected to the cell plate line PL. This configuration will be described later in detail with reference to
FIGS. 22 and 23
. The memory cell structure of the ferroelectric memory strongly resembles the memory cell structure of a DRAM basically, but is different from that of the DRAM, which has a capacitor composed of a paraelectric, especially in that the ferroelectric capacitor C has a residual polarization characteristic (hysteresis characteristic)
FIG. 24
is a view illustrating the residual polarization characteristic of a general ferroelectric capacitor C. The ferroelectric capacitor C generates positive residual polarization at point B or negative residual polarization at point D shown in
FIG. 24
, depending on the high/low relationship between the voltage applied to the first electrode of the ferroelectric capacitor C from the bit line BL via the memory cell transistor Q and the voltage applied to the second electrode of the ferroelectric capacitor C from the cell plate line PL.
For example, suppose it is defined during writing that the residual polarization is positive when the voltage applied to the first electrode of the ferroelectric capacitor C is a supply voltage VDD and the voltage applied to the second electrode thereof is a ground voltage,VSS (≈0), and that the residual polarization amount is L when the voltage applied to the first electrode of the ferroelectric capacitor C is the ground voltage VSS and the voltage applied to the second electrode thereof is the supply voltage VDD. During reading, when the potential at the ferroelectric capacitor C is read to the bit line BL by turning ON the memory cell transistor Q, the voltage at the bit line BL is high or low depending on whether the polarization of the ferroelectric capacitor C is positive or negative. The difference between the potential at the bit line and a reference potential is amplified by a sense amplifier (not shown), to allow the data to be determined “1” or “0”.
In a one-transistor one-capacitor (1T1C) memory cell, one common reference cell is provided for a number of cells (for example, one for 256 cells), and a sense amplifier amplifies the difference between the reference potential read from the reference cell and each potential read to the bit line, to determine data “1” or “0” depending on which potential is higher.
In a two-transistor two-capacitor (2T2C) memory cell, one memory cell is configured as follows. For example, in the structure shown in
FIG. 21
, one memory cell is composed of two transistors Qaa and Qba connected to one word line WLa and two bit lines BLa and BLb, and two ferroelectric capacitors Caa and Cba. Data “1” is allocated and stored when the polarization of the ferroelectric capacitor Caa is positive and the polarization of the ferroelectric capacitor Cba is negative, and data “0” is allocated and stored when the polarization of the ferroelectric capacitor Caa is negative and the polarization of the ferroelectric capacitor Cba is positive. During reading, the potential difference between the two bit lines BLa and BLb is amplified with a sense amplifier (not shown) provided between the two bit lines BLa and BLb. Data “1” or “0” is determined depending on which potential is higher.
The structure of the memory cell array of the ferroelectric memory on a semiconductor substrate will be described.
FIG. 22
is a top view of the conventional ferroelectric memory where only the structure of the memory cell array located on a semiconductor substrate is illustrated and an interlayer insulating film is transparent.
As shown in
FIGS. 22 and 23
, active regions (source/drain regions, channel regions, and the like) of the transistors Q are formed in a semiconductor substrate
100
. The word lines WL made of polysilicon, which serve as gate electrodes at positions above the channel regions, extend above the semiconductor substrate
100
. Capacitance portions are formed above the respective source regions of the transistors Q. Each capacitance portion includes: a bottom electrode BE (first electrode) of the ferroelectric capacitor C, made of any of metals including metals of platinum and iridium group, which is an equivalent of a storage node of a DRAM; a ferroelectric film FD made of KNO
3
, PbLa
2
O
3
—ZrO
2
—TiO
2
(PLZT), PbTiO
3
—PbZrO
3
(PZT), or the like; and a top electrode TE (second electrode) made of any of metals including metals of platinum and iridium group. The bottom electrode BE of the capacitance portion is connected to the source of the memory cell transistor Q via a contact CS. This structure of the capacitance portion is called a stacked capacitor structure. The top electrodes TE constitute part of the cell plate lines PL that extend in parallel with the word lines WL as shown in FIG.
22
. Above the capacitance portions, the bit lines BL extend in a direction parallel with the cross section of
FIG. 23
, and connected to the drain regions of the memory cell transistors Q via contacts CW. An interlayer insulating film
101
is formed over the semiconductor substrate
100
burying the contacts CS, the bottom electrodes BE, the ferroelectric films FD, the top electrodes TE (cell plate lines PL), the contacts CW, the bit lines BL, and the like. A LOCOS isolation insulation film electrically isolates every opposing source regions of adjacent memory cell transistors from each other. The portions other than the active regions enclosed by the rectangles in
FIG. 22
represent the LOCOS isolation film.
Referring to
FIGS. 21 through 23
, in the memory cell array of the conventional ferroelectric memory, one cell plate line PL is provided for each word line WL. Such cell plate lines PL occupy a large area of the memory cell

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