Ferroelectric memory device

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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Details

C365S065000, C365S149000, C365S225700

Reexamination Certificate

active

07965536

ABSTRACT:
According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor.

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patent: 6320782 (2001-11-01), Takashima
patent: 6473331 (2002-10-01), Takashima
patent: 6657882 (2003-12-01), Takashima
patent: 7102908 (2006-09-01), Thomas et al.
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patent: H03-162798 (1991-07-01), None
patent: 2006-134529 (2006-05-01), None
Hidehiro Shiga et al., “A 1.6GB/s DDR2 128Mb Chain FeRAM with Scalable Octal Bitline and Sensing Schemes”, ISSCC Dig Tech Papers. pp. 464-465, Feb. 2009.
Explanation of Non-English Language References.

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