Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
1999-06-30
2001-07-17
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06262909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory device, and more particularly to a ferroelectric memory device in which a switching transistor is coupled to a plurality of ferroelectric capacitors, thereby outputting a plurality of information when an address signal is inputted.
2. Description of the Prior Art
It is well known that the ferroelectric memory element has been gaining importance as a next generation memory since it has non-volatile characteristics. The memory including a plurality of ferroelectric material can be a non-volatile memory by using the characteristics that maintain a constant charge amount for the ferroelectric material characteristics even if the potential difference in both ends of a capacitor does not exist.
FIG. 1A
shows a symbol of a ferroelectric capacitor, and
FIG. 1B
is a graph showing the charge amount vs voltage curve where the ferroelectric capacitor has a hysterisis relationship between the voltage and the charge. As shown in the hysterisis curve, even if the voltage in both ends of a capacitor is 0V, binary information can be memorized since the constant charge amount is maintained as a state “P1” or “P2”, unlike linear capacitors. This is due to the fact that the atomic arrangement of the ferroelectric material is polarized when the electric field is applied to and cut off from the ferroelectric material. This is the very reason that the memory used by the ferroelectric capacitor as a storage means, can be a non-volatile memory. Another feature of the ferroelectric capacitor is that the charge amount curve according to the voltage or potential has a hysterisis relationship. Any voltage which is lower than −3V is applied to the ferroelectric capacitor, the polarization state of the ferroelectric material is changed and then the charge amount is moved to state “P3” as depicted in FIG.
1
B. While the minus voltage is changed to plus voltage, the charge amount is moved to state “P4” through state “P2”. Thus, the charge amount for the ferroelectric capacitor is changed along with arrow direction in accordance with the voltage variation as depicted by the arrow direction in FIG.
1
B.
There are many cases wherein the ferroelectric capacitors are applied to the memory elements. A ferroelectric memory cell generally includes one witching transistor and one dielectric capacitor. Also, a memory array having a plurality of memory cell includes a plurality of word lines for driving each switching transistor and bit lines for sensing and amplifying the charge amount stored in capacitors. Each word line and bit line is connected so that they cross each other. Each word line is connected to the gate of each switching transistor to control the switching on/off operation, each bit line is connected to a source of each switching transistor, and one end of each dielectric capacitor is connected to a drain of each switching transistor, respectively. The other end of the electric capacitor is connected to each plate line, respectively. In order to detect or store the charge which is stored in a dielectric capacitor in the ferroelectric memory element, an electric field is applied to both ends of each capacitor.
FIG. 2
is a circuit diagram showing a related ferroelectric memory device including a switching transistor and a dielectric capacitor. Here, one bit information of “0” or “1” digit is stored in the capacitor. But, an address signal is generally applied to the memory device, and a plurality of output signals, (i.g.
1
,
8
,
16
,
32
, . . . etc.) are outputted by driving switching transistors corresponding to the number of the output signals. For example, if a memory device, which is set to output 8 bits (i.e. 1 byte) at a certain time, is accessed by an input address, 8 switching transistors are turned on in order to output the corresponding data. However, as the memory device requires a large numner of output data, the level of the circuit complexity may be highly increased in proportion to the number of the switching transistors. Accordingly, there are problems including the increase of power consumption and the enlargement of the total chip area of the memory device which leads to further circuit complexity.
SUMMARY OF THE INVENTION
Therefore, an objective of the present invention is to solve the disadvantages involved in the prior art, and to provide a ferroelectric memory device having a memory cell structure where a plurality of ferroelectric capacitors are connected to one switching transistor, and a plurality of data are outputted according to one address input.
The other objective of the present invention is to provide a ferroelectric memory device having a memory cell structure where both a chip area is reduced and a plurality of information is obtained by using the minimum switching transistors.
In order to achieve the above objectives, a ferroelectric memory device is provided, comprising a plurality of word lines for driving a corresponding memory cell in accordance with an input address; a plurality of bit lines crossing said word lines, respectively; a plurality of switching transistors connected both to said bit lines and said work lines, respectively; and a plurality of dielectric capacitors whose one end coupled to a node of said switching transistor, respectively; wherein a plurality of data are outputted by selecting one memory cell including at least one switching transistor corresponding to the plurality of switching transistor, and the plurality of dielectric capacitors.
It is desired that a memory cell of a ferroelectric memory device according to the present invention includes a switching transistor and a plurality of dielectric capacitors, and the number of each said switching transistor is determined by 2
N
(N=0,1,2,3 . . .) sequence such as 2, 4, 6, 8 . . . etc.
Further, the ferroelectric memory device according to the present invention further includes a plurality of plate lines connected to the other ends of the plurality of dielectric capacitors, respectively; and a plurality of sensing amplifiers, coupled to said plate lines, respectively, for sensing and amplifying the voltage variation of each said plate line.
Here, cell data are sensed and amplified through each plate line and then are outputted.
In order to achieve another objective, a ferroelectric memory device is provided, comprising a plurality of word lines for driving a corresponding memory cell in accordance with an input address; a plurality of bit lines crossing said word lines, respectively; a plurality of first switching transistors connected both to bit lines and said work lines, respectively; a plurality of second switching transistors connected in common to said word lines and said bit lines which are connected to said first switching transistors, respectively; a plurality of first dielectric capacitor group whereine each capacitor is connected in common to one node of said first switching transistor, respectively; a plurality of second dielectric capacitor group wherein each capacitor is connected in common to one node of said second switching transistor, respectively; wherein a plurality of output data are outputted by selecting a memory cell.
Further, the ferroelectric memory device according to the present invention further includes a plurality of plate lines connected to the other ends of the plurality of first and second dielectric capacitors, respectively; and a plurality of sensing amplifiers, coupled to said plate lines, respectively, for sensing and amplifying a voltage variation of each said plate line.
Here, cell data are sensed and amplified through each plate line and then are outputted, and the sensing amplifiers are connected in common to a plurality of plate lines which belong to the other column.
REFERENCES:
patent: 5392234 (1995-02-01), Hirano et al.
patent: 5600587 (1997-02-01), Koike
patent: 5926413 (1999-07-01), Yamada et al.
patent: 6038160 (2000-03-01), Nakane et al.
Kang Woo Soon
Kye Hoon Woo
Hyundai Electronics Industries Co,. Ltd.
Nath Gary M.
Nath & Associates PLLC
Nguyen Tan T.
Novick Harold L.
LandOfFree
Ferroelectric memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ferroelectric memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2568038