Ferroelectric memory configuration

Details Ferroelectric memory configuration Ferroelectric memory configuration

1999-11-15

2000-10-24

Nelms, David

Static information storage and retrieval

Systems using particular element

Ferroelectric

36518907, G11C 1122

Patent

active

061377120

ABSTRACT:
The invention relates to a memory configuration comprising a multiplicity of memory cells. Each of the memory cells has at least one ferroelectric storage capacitor and a selection transistor. The memory cells are addressed via word lines and bit line pairs. It is possible for a reference signal obtained from a reference cell pair via a bit line pair to be compared with a read signal from a memory cell in a sense amplifier. The sense amplifier is thereby assigned two bit line pairs connected in such a way that the reference signal is applied via the first bit line pair and, at the same time, the read signal is applied via the second bit line pair to the sense amplifier.

REFERENCES:
patent: 5218566 (1993-06-01), Papaliolios
patent: 5828615 (1998-10-01), Mukunoki et al.
patent: 5969979 (1999-10-01), Hirano
patent: 6058040 (2000-05-01), Tada

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