Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-07
2003-12-30
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S300000, C257S310000
Reexamination Certificate
active
06670661
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a memory cell configuration for the nonvolatile storage of data. For the nonvolatile storage of data, memory cell configurations have been proposed in which each memory cell has at least one ferroelectric transistor (see European Patent EP 0 566 585 B1, corresponding to U.S. Pat. No. 5,471,417 to Krautschneider). The term ferroelectric transistor in such a case refers to a transistor having two source/drain regions, a channel region, and a gate electrode. A ferroelectric layer, that is to say, a layer made of ferroelectric material, is provided between the gate electrode and the channel region. The conductivity of the transistor is dependent on the polarization state of the layer made of ferroelectric material. Such ferroelectric transistors are being investigated with regard to nonvolatile memories. In such a case, two different logic values of a digital information item are assigned two different polarization states of the layer made of ferroelectric material.
In the memory cell configuration disclosed in European Patent EP 0 566 585 B1, it is proposed to apply a voltage individually for the different memory cells below the ferroelectric layer at the substrate, in order, when writing information to one memory cell, to avoid altering the information in other, non-selected memory cells. To that end, there is provided below the active transistor region a doped layer, which is insulated from the general substrate by pn junctions and is insulated from adjacent memory cells by insulation regions, which represents an individual substrate for the individual ferroelectric transistor.
Another memory cell configuration with ferroelectric transistors as memory cells has been proposed in T. Nakamura, Y. Nakao, A. Kamisawa, H. Takasu: A Single Transistor Ferroelectric Memory Cell, IEEE, 1995, pages 68 to 69. Set forth in the document is that each of the ferroelectric transistors is connected between a supply voltage line and a bit line. Selection is effected through a back gate. In such a case, the ferroelectric transistors used have a floating gate electrode between the ferroelectric layer and the gate oxide, the charge of which electrode is controlled by the polarization state of the ferroelectric layer.
It has been shown that in such memory cell configurations, when the information is read, a voltage is also dropped across non-selected memory cells, which voltage can lead to corruption of the information stored in the individual memory cells. Such corruption is attributed to the fact that umklapp or fold-over processes of the domains in ferroelectric materials are of a statistical nature and can be brought about even at low voltages.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that has memory cells each with a ferroelectric transistor in which alteration of the written-in information during the reading operation is avoided.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a memory cell configuration, including a semiconductor substrate having a surface, strip-type doped well regions, and integrated memory cells, each of the memory cells having a ferroelectric transistor, a diode structure, and word lines running substantially parallel to one another. The ferroelectric transistor has a first source/drain region, a second source/drain region, a first gate intermediate layer and a first gate electrode disposed at the surface of the substrate between the first and second source/drain regions, the first gate intermediate layer containing at least one ferroelectric layer, a second gate intermediate layer and a second gate electrode disposed between the first and second source/drain regions in a direction of a connecting line between the first and second source/drain regions, the second gate intermediate layer containing a dielectric layer, and, beside the first gate intermediate layer, the second gate intermediate layer, the first gate electrode, and the second gate electrode connected to one another through the diode structure. The second gate electrode is respectively connected to one of the word lines and the strip-type doped well regions cross the word lines and respectively run in a region between the first and second source/drain regions of the ferroelectric transistor.
With the objects of the invention in view, there is also provided a memory cell configuration where the ferroelectric transistor has a second gate intermediate layer and a second gate electrode disposed between the first and second source/drain regions.
With the objects of the invention in view, there is also provided a memory cell configuration where the ferroelectric transistor has a second gate intermediate layer and a second gate electrode disposed between the first and second source/drain regions substantially along a line connecting the first and second source/drain regions.
In the memory cell configuration, a multiplicity of memory cells, each having a ferroelectric transistor, are provided in an integrated manner in a semiconductor substrate. The respective ferroelectric transistor includes two source/drain regions. Between the source/drain regions a first gate intermediate layer and a first gate electrode are disposed at the surface of the semiconductor substrate, the first gate intermediate layer containing at least one ferroelectric layer, and between which a second gate intermediate layer and a second gate electrode are disposed in the direction of a connecting line between the source/drain regions. Beside the first gate intermediate layer, the second gate intermediate layer containing a dielectric layer, the first gate electrode, and the second gate electrode are connected to one another through a diode structure. Furthermore, word lines that substantially run parallel are provided in the memory cell configuration, the second gate electrode in each case being connected to one of the word lines. Furthermore, strip-type doped well regions are provided in the semiconductor substrate, which well regions cross the word lines and in each case run in the region between the source/drain regions of the ferroelectric transistors.
In the memory cell configuration, one of the memory cells is selected by the associated word line and the associated strip-type doped well region. The non-selected strip-type doped well regions and word lines have applied to them voltage levels such that the polarization state of the ferroelectric layer in the non-selected memory cells is not altered. The provision of the strip-type doped well regions allows the application of an individual substrate voltage to the ferroelectric transistors disposed along the respective strip-type doped well region.
Because, in the ferroelectric transistor, the first gate electrode and the second gate electrode are disposed respectively beside one another along the connecting line between the source/drain regions, the channel region of the ferroelectric transistor is subdivided. One part of the channel region, which is disposed beneath the first gate electrode, can be driven by the charge that is effective on the first gate electrode. Another part of the channel region, which is disposed beneath the second gate electrode, can be driven by the charge that is effective on the second gate electrode. A current can flow between the source/drain regions only when both the part of the channel region below the first gate electrode and the part of the channel region below the second gate electrode are conducting.
The diode structure is connected in a polarity such that when a voltage is present at the second gate electrode that controls the conductivity of the channel region beneath the second gate electrode, the diode structure turns off and the first gate electrode is thereby isolated from the voltage. The configuration ensures that the voltage for driving the second
Bachhofer Harald
Haneder Thomas Peter
Dickey Thomas L
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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