Ferroelectric memory cell fabrication method

Details Ferroelectric memory cell fabrication method Ferroelectric memory cell fabrication method

1999-12-15

2002-01-29

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S313000, C430S317000, C430S318000, C430S320000, C257S295000, C438S003000, C438S692000, C216S052000

Reexamination Certificate

active

06342337

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a method of fabricating ferroelectric memory cells.
2. Description of Related Art
Ferroelectric bodies are materials that exhibit spontaneous polarization which can be reversed by an electric field. Such materials are used in forming semiconductor memory devices. For example, by replacing the ordinary dielectric material in DRAM capacitors with ferroelectric material, ferroelectric memory cells are configured.
The 1T1C and 2T2C type structures are known as general structures for such ferroelectric memory cells. In the 2T2C structure, two transistors and two capacitors are combined to configure one memory cell. What is characteristic of this 2T2C ferroelectric memory cell is that conflicting data, like an inverted signal and a non-inverted signal, are written to two ferroelectric capacitors, that strong durability is exhibited to fatigue wherein the polarization quantity is diminished by rewrite frequency, and that the stable operation of the memory cell involved is secured. However, the surface area occupied by each cell is large, making the 2T2C structure unsuitable for high integration.
Meanwhile, the 1T1C structure is being developed in the interest of achieving high integration by reducing cell occupation area, and research on this structure is currently being ongoing. Ferroelectric memory cells having the 1T1C structure present many problems that need to be resolved, such as the necessity of generating a reference potential in order to distinguish between a binary “1” and a binary “0,” and the necessity of making further improvements in order to obtain stable operation in these memory cells.
In order to enhance ferroelectric memory cell integration, the capacitors wherein the ferroelectric material is used must be made very minute. The technology required for such microfabrication is dry etching technology. When ferroelectric materials and the electrode materials used in the capacitors are etched to form patterns thereof, respectively, the configuring elements react with the etching gas to produce reaction products. In most cases, these reaction products have a low vapor pressure, wherefore the reaction products build up on the patterns, without being vaporized. As a result, the desired minute or fine patterns cannot be formed.
As is commonly known, platinum (Pt) has been used up until now as the primary electrode material for evaluating ferroelectric thin films. Because platinum does not readily form reaction products with the etching gas, etching residue builds up, during etching, in the peripheral areas on the upper surface of the platinum patterns formed. (See reference “S. Onishi, et al.: ‘technology. dig. Int. Electron Devices Meet., (IEDM)’ 1994, pp 843-846.”)
Meanwhile, when SrBi
2
Ta
2
O
9
(abbreviated SBT) is used as the ferroelectric material, the etching of this material with BCl
3
, which is more reductive than CL
2
, is known. BCl
3
provides an etching rate that is better than that provided by Cl
2
. When BCl
3
is used in this etching, however, the edge surfaces of the patterns formed do not become perpendicular surfaces but rather become sloped or bevel surfaces. When the pattern edge surfaces are sloped surfaces, adverse effects are imposed on the ferroelectric material configuring the capacitors. (See reference “Y. Maejima, et al.: ‘Symposium on VLSI Technology Digest of Technical Papers,’ 1997, pp 137-138.”)
As discussed in the foregoing, the build-up of reaction products and the build-up of etching residue hinders the minute processing or microfabrictation of ferroelectric materials and electrode materials.
There is also a danger that the reaction products built up on the electrode patterns formed will cause current leakage to the capacitor periphery.
Also, the edge regions of ferroelectric patterns to be formed by dry etching are exposed to plasma during the etching. As a consequence, the crystalline structure of and atomic arrangement in the ferroelectric material are greatly damaged by that plasma. For this reason, when capacitors are formed using the ferroelectric material that has been damaged in this manner, there is a danger that the electrical characteristics such as the amount of charge therein (i.e. the polarization quantity) will be different from the amount of charge designed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for microfabricating or minutely processing electrode materials and ferroelectric materials to form ferroelectric memory cells without producing build-up and without damaging the ferroelectric patterns formed.
In a first aspect of the present invention, a first electrode and a dielectric film that configure a capacitor are formed using a CMP (chemical mechanical polishing) technique instead of using an etching technique.
More specifically, according to this first aspect, a method of fabricating a ferroelectric memory cell comprising a first and a second electrode, and a ferroelectric film interposed between that first and second electrode, includes following steps of:
forming a preparatory first electrode layer either on or above an underlayer;
removing a portion of the preparatory first electrode layer, using a first CMP (chemical mechanical polishing) technique, and forming the first electrode by the remaining or residual portion of the preparatory first electrode layer;
forming a preparatory ferroelectric film above the underlayer on which the first electrode is formed, causing a portion thereof to come in contact with the first electrode; and
removing that portion of the preparatory ferroelectric film that does not come in contact with the first electrode using a second CMP (chemical mechanical polishing) technique, and forming the ferroelectric film with the remaining or residual portion of the preparatory ferroelectric film.
According to this method, the first electrode material and the ferroelectric material are minutely of finely patterned by CMP to form the first electrode and the ferroelectric film, wherefore there will be no adherence of build-up matter on the patterns formed, and the edge surfaces of the ferroelectric film can be formed as perpendicular surfaces. Accordingly, it is possible to obtain capacitors that are highly reliable.
According to a second aspect of the present invention, after forming the ferroelectric film, a second electrode as a member of a capacitor is formed using a CMP (chemical mechanical polishing) technique instead of using an etching technique.
More specifically, a method for fabricating a ferroelectric memory cell based on this second aspect comprises steps of:
forming a preparatory second electrode layer above the underlayer on which the ferroelectric film has been formed, causing a portion thereof to come in contact with the ferroelectric film; and
removing the portion of the preparatory second electrode layer that does not make contact with the ferroelectric film, using a third CMP (chemical mechanical polishing) technique, and forming the second electrode with the remaining or residual portion of the preparatory second electrode layer.
According to this method, minute or fine patterning is done with CMP to form the second electrode, wherefore there will be no build-up matter adhering to the pattern formed. Accordingly, capacitors can be obtained which are highly reliable.
According to a third aspect of the present invention, after forming the ferroelectric film, the second electrode as a member of the capacitor is formed using an etching technique.
More specifically, a method for fabricating a ferroelectric memory cell based on this third aspect comprises steps of:
forming a preparatory second electrode layer above the underlayer on which the ferroelectric film has been formed, causing a portion thereof to come in contact with the ferroelectric film; and
removing the portion of the preparatory second electrode layer that does not make contact with the ferroelectric film, using a photolithographic etchin

Affiliated with

Also associated with

Rating

Ferroelectric memory cell fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ferroelectric memory cell fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory cell fabrication method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2868816