Ferroelectric memory cell arrangement

Details Ferroelectric memory cell arrangement Ferroelectric memory cell arrangement

1993-07-09

1995-11-28

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Ferroelectric

36518513, 257295, 257330, G11C 1122

Patent

active

054714176

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates generally to non-volatile memory cells.
2. Description of the Related Art
Memory cells comprising semiconductor components which are operated as dynamic or static memories generally loose the stored information after the supply voltage has been switched off. In the case of a spontaneous voltage failure, all data stored in these memories are erased.
In the case of memory cell arrangements which are built up from dynamic single-transistor cells, the additional disadvantage is that a refresh must be carried out at regular time intervals for compensating for the charge drained by leakage currents. This increases power consumption and circuit complexity.
Furthermore, dynamic memories are sensitive against alpha radiation. This produces error bits.
It is known (see for example S. M. Sze, Semiconductor Devices, John Wiley & Sons 1985, p. 490), to use so-called electrically programmable memories (EPROM) or electrically programmable and erasable memories (EEPROM) for permanent storage. In these non-volatile memories, the load is retained when the voltage supply is switched off. In these memories, the information is stored with the aid of the charging-up of a floating gate by the injection of hot charge carriers or Fowler-Nordheim tunnel current or by charging up impurity traps and dielectric boundary layers (NMOS transistors). In this arrangement, the floating gate or the impurity traps are surrounded by a high-quality insulator so that there is virtually no charge drainage.
A disadvantage of these memories is that the write process takes place with time constants in the millisecond range, that is to say is relatively slow. A further disadvantage consists in that the high-quality insulator becomes fatigued after about 10.sup.3 to 10.sup.6 write cycles. After that, no further permanent charge storage can then be carried out.


SUMMARY OF THE INVENTION

The invention is based on the problem of specifying a memory cell arrangement and a method for operating it, in which the stored information is retained when the supply voltage fails and in which the write process is faster than in the known arrangements.
According to the invention, the problem is solved by means of a memory cell arrangement having the following features:
a) in a semiconductor substrate, at least one field-effect transistor having a source region, a drain region, a gate dielectric and a gate electrode is provided as a memory cell, the semiconductor substrate being doped with a first type of conductivity and the source region and the drain region being doped with a second type of conductivity which is opposite to the first type of conductivity, and
b) the gate dielectric contains at least one ferroelectric layer.
By using a ferroelectric layer as gate dielectric, the memory cell arrangement according to the invention avoids the abovementioned disadvantages of the prior art.
Ferroelectric materials such as, for example, lead zirconate titanate, can be remanently polarized by applying an electrical field which is greater than a material-specific saturation field strength. The sign of the remanent polarization can be changed by reversing the direction of the electrical field. A field-effect transistor which contains a ferroelectric layer as a gate dielectric exhibits one of two different threshold voltages at which current flow starts depending on the sign of the polarization of the ferroelectric layer.
This property is utilized in the memory cell arrangement according to the invention for building up a memory cell comprising a ferroelectric transistor. The logic states "0" and "1" are assigned to the two alternate threshold voltages.
Since the state of polarization of the ferroelectric layer is retained even without an external field, no loss of information occurs after the supply voltage has been switched off. In addition, the memory cell arrangement according to the invention does not require any refresh and the memory cells are insensitive to alpha radiation.
In the m

REFERENCES:
patent: 4427989 (1984-01-01), Anantha
patent: 4829351 (1989-05-01), Engles et al.
patent: 4920397 (1990-04-01), Ishijima
patent: 5198994 (1993-03-01), Natori
patent: 5237188 (1993-08-01), Iwai
"A Metal-Insulator-Semiconductor (MIS) Device Using a Ferroelectric Polymer Thin Film in the Gate Insulator", Japanese Journal of Applied Physics, vol. 25, No. 4, Apr. 1986, pp. 590-594.
Proceedings of the IEEE, vol. 64, No.7, 1976, p. 1053.
"Integrated Devices", Semiconductor Devices Physics and Technology, pp. 486-490. S. M. Sze. 1981.

Affiliated with

Also associated with

Rating

Ferroelectric memory cell arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ferroelectric memory cell arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory cell arrangement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2018205