Ferroelectric memory and method of testing the same

Details Ferroelectric memory and method of testing the same Ferroelectric memory and method of testing the same

1999-04-22

2001-05-08

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S190000, C365S210130

Reexamination Certificate

active

06229728

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a ferroelectric memory and a method of testing a ferroelectric memory.
2. Description of the Related Art
FIG. 1
is a circuit diagram of a memory cell of a one-transistor/one-capacitor type, which is an example of memory cells of a ferroelectric memory. In
FIG. 1
, WL denotes a word line, PL denotes a plate line, BL denotes a bit line, Cbit denotes a parasitic capacitor,
1
indicates a ferroelectric capacitor, and
2
indicates an n-channel MOS (nMOS) transistor functioning as a switch element.
Data is written into the memory cell as follows. The word line WL is selected and the nMOS transistor
2
is thus turned on. Then, an electric field is applied to the ferroelectric capacitor
1
using the bit line BL and the plate line PL.
For example, data “1” is written into the memory cell, a potential VBL of the bit line BL is set higher than a potential VPL of the plate line PL in the state in which the nMOS transistor
2
is in the ON state. Hence, a remanent polarization oriented downwards in the figure from the bit line BL to the plate line PL remains. In contrast, data “0” is written into the memory cell, the potential VBL of the bit line BL is set lower than the potential VPL of the plate line PL in the state in which the nMOS transistor
2
is in the ON state. Hence, a remanent polarization oriented upwards in the figure from the plate line PL to the bit line BL remains.
The above memory operation can be represented as a hysteresis characteristic of the ferroelectric capacitor
1
shown in FIG.
2
. The horizontal axis of the graph of
FIG. 2
denotes a voltage V applied across the ferroelectric capacitor
1
, and is defined such that V=VPL−VBL. The vertical axis of the graph denotes polarization. The plus side of the vertical axis is defined as an upward polarization, and the minus side thereof is defined as a downward polarization.
Hence, a minus remanent polarization −Ps remains when the electric field applied across the ferroelectric capacitor
1
is zero (when VPL=VBL) corresponds to a state in which data “1” is stored, and a plus remanent polarization Ps corresponds to a state in which data “0” is stored.
Data is read from the memory cell shown in
FIG. 1
as follows. The bit line BL is precharged to 0 V so as to be set in a high-impedance state. Next, the word line WL is selected to turn on the nMOS transistor
2
. Then, the potential of the plate line PL is changed to a power supply voltage VCC from 0 V. Hence, a charge dependent on the state of polarization of the ferroelectric capacitor
1
is moved from the ferroelectric capacitor
1
to the bit line BL. Thus, the original charge is divided into parts respectively stored in the ferroelectric capacitor
1
and the parasitic capacitor Cbit. Thus, a potential VBL
0
or VBL
1
dependent on the stored data “0” or “1” appears on the bit line BL.
FIG. 3
is a graph of the levels of the potentials VBL
0
and VBL
1
of the bit line BL. When the memory cell shown in
FIG. 1
stores data “0”, the potential VBL
0
of the bit line BL can be obtained from the cross point at which the curve of the hysteresis characteristic of the ferroelectric capacitor
1
and a load line LO of the parasitic capacitor Cbit of the bit line BL cross each other.
In contrast, when the memory cell shown in
FIG. 1
stores data “1”, the potential VBL
1
of the bit line BL can be obtained from the cross point at which the curve of the hysteresis characteristic of the ferroelectric capacitor
1
and a load line L
1
of the parasitic capacitor Cbit of the bit line BL cross each other.
When the stored data is “0”, the polarized state of the ferroelectric capacitor
1
is maintained after the data is read out. In contrast, when the stored data is 1, the polarization of the ferroelectric capacitor
1
is inverted, so that rewriting of the data is needed. The data write can automatically be performed by a sense amplifier as in the case of a DRAM (Dynamic Random Access Memory).
FIG. 4
is a circuit diagram of a part of a cell array of a conventional ferroelectric memory equipped with one-capacitor/one-transistor type memory cells. In
FIG. 4
, WLon and WLen respectively denote word lines, PLcn denotes a plate line, BLn and /BLn respectively denote bit lines,
3
and
4
respectively indicate memory cells,
5
and
6
respectively ferroelectric capacitors serving as recording media, and
7
and
8
respectively nMOS transistors serving as switch elements. Further, RWLo and RWLe respectively denote word lines, RPLc denotes a plate line,
9
indicates a reference cell which outputs a reference potential Vref to the bit line /BLn,
10
indicates a reference cell which outputs the reference potential Vref to the bit line BLn, and
11
indicates a sense amplifier which amplifies the potential difference between the bit lines BLn and /BLn and thus detects the stored data read out from the selected memory cell.
The stored data read out to the bit line BLn is compared with the reference potential Vref output to the bit line /BLn from the reference cell
9
, and the logical value thereof is thus decided. The stored data read out to the bit line /BLn is compared with the reference potential Vref output to the bit line BLn from the reference cell
10
, and the logical value thereof is thus decided.
FIG. 5
is a circuit diagram of the conventional reference cell. In
FIG. 5
, RWL denotes a word line, RPL denotes a plate line, BL denotes a bit line, Cbit denotes a parasitic capacitor of the bit line BL,
12
indicates a ferroelectric capacitor having a larger area than the ferroelectric capacitor of the memory cell, and
13
indicates an nMOS transistor serving as a switch element.
When the reference cell shown in
FIG. 5
is used, data “0” is written into the ferroelectric capacitor
12
in which an upward remanent polarization oriented upward in the figure remains. When the reference potential Vref is generated, the bit line BL is precharged to 0 V and is set to the high-impedance state. Then, the word line RWL is selected and the nMOS transistor
13
is turned on. Hence, the plate line PL is set to the power supply potential VCC from 0 V.
With the above operation, a charge dependent on the magnitude of the remanent polarization of the ferroelectric capacitor
12
is moved to the bit line BL from the ferroelectric capacitor
12
. Thus, the total charge is divided into parts respectively stored in the ferroelectric capacitor
12
and the parasitic capacitor Cbit of the bit line BL. Hence, the reference potential Vref appears on the bit line BL.
FIG. 6
is a graph showing the level of the reference potential Vref output by the reference cell shown in FIG.
5
. The level of the reference cell Vref can be obtained from the cross point at which the curve of the hysteresis characteristic of the ferroelectric capacitor
12
and a load line RL
0
of the parasitic capacitor Cbit of the bit line BL cross each other.
FIG. 7
shows another configuration of the reference cell. In
FIG. 7
, RWL denotes a word line, RPL denotes a plate line, BL denotes a bit line, Cbit denotes a parasitic capacitor of the bit line BL,
14
indicates a ferroelectric capacitor having a larger area than the ferroelectric capacitor of the memory cell,
15
indicates an nMOS transistor serving as a switch element,
16
indicates a p-channel (pMOS) transistor serving as a switch element,
17
is a VCC line, and PCL denotes a precharge control line.
When the reference cell shown in
FIG. 7
is used, the pMOS transistor
16
is maintained in the on state by controlling the precharge control line PCL during a non-selected state. Hence, a node
18
is precharged to the power supply potential VCC, and a downward remanent polarization in the figure is generated in the parasitic capacitor
14
.
When the reference voltage Vref is generated, the bit line BL is precharged to 0 V, and is set to the high-impedance state. Further, the pMOS transistor
16
is turned off, and the word line RWL is se

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