Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
1997-11-24
2002-03-12
Fears, Terrell W. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189011
Reexamination Certificate
active
06356475
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a ferroelectric memory and a method of reading out data from the ferroelectric memory, and more particularly, to a ferroelectric memory having memory cells in which ferroelectric capacitors formed by ferroelectric substances such as Pb(Zr, Ti)O
3
are used as storage mediums.
The present invention is also directed to a ferroelectric memory and a method of reading out data from the ferroelectric memory so as to carry out a stable reading-out operation by increasing a signal margin for reading out the data.
2. Description of the Related Art
A semiconductor memory using ferroelectric capacitors formed by ferroelectric substances such as Pb(Zr, Ti)O
3
is a non-volatile memory and has a feature of having substantially the same writing-and-reading speed as that of a DRAM. Therefore, it is assumed that a demand for a large number of ferroelectric memories will increase in the future.
With respect to an operation method of the ferroelectric memory, several kinds of methods are known, and these operation methods are disclosed, for example, in U.S. Pat. No. 4,873,664 (Ramtron), and Japanese Patent Publication 7-13877 (Toshiba CO. LTD). In theses methods, by applying a voltage to the ferroelectric capacitor, the data is discriminated according to an inversion of a polarization of the ferroelectric capacitor.
When a memory cell is constructed with one transistor and one capacitor, in order to determine whether or not the polarization is inverted, a reference circuit (dummy cell) generating an intermediate load (or voltage) needs to be constructed with the ferroelectric capacitor.
However, characteristics of this reference circuit may be easily varied by process dispersion of a ferroelectric film and fatigue due to inversion (referred to as inversion fatigue, hereinafter) of the ferroelectric capacitor. Therefore, there is a problem in that the signal margin is reduced, and a stable reading-out operation may not be conducted.
In the following, a more detailed description will be given of the operation of the above-discussed prior-art ferroelectric memory.
FIG. 1
shows a schematic diagram for illustrating a part of one embodiment of a prior-art ferroelectric memory. The ferroelectric memory shown in
FIG. 1
includes memory cells
1
,
2
, which have ferroelectric capacitors
3
,
4
, and transistors
5
,
6
forming transmission gates. The transistors
5
,
6
are so-called cell transistors.
In
FIG. 1
, symbols “WL
0
and WL
1
” indicate word lines for selecting a memory cell, and the symbols “PL
0
and PL
1
” indicate plate lines for driving a plate electrode of the ferroelectric capacitor of a selected memory cell.
The ferroelectric memory shown in
FIG. 1
further includes dummy cells
7
,
8
which have ferroelectric capacitors
9
,
10
having an overlapped area of opposite electrodes half that of the ferroelectric capacitors
3
,
4
, and cell transistors
11
,
12
. In this embodiment, into the ferroelectric capacitors
9
,
10
, a logic “1” is written.
In
FIG. 1
, symbols “DWL
0
and DWL
1
” indicate word lines for selecting the dummy cell, and the symbols “DPL
0
and DPL
1
” indicate plate lines for driving a plate electrode of the ferroelectric capacitor of a selected dummy cell.
Further, symbols “BL and /BL” indicate bit lines forming data lines (data transmission lines), and the ferroelectric memory further includes a sense amplifier which amplifies a voltage difference between the bit lines BL and /BL when data is read out, and detects data read out from the selected memory cell.
FIG.
2
and
FIG. 3
show illustrations for explaining a data-writing sequence in the memory cell of the ferroelectric memory. In these drawings, an example of the data-writing sequence in the memory cell
1
is shown. A horizontal axis indicates a voltage between the bit line BL and the plate line PL
0
, namely, a voltage V
BL
of the bit line BL to an earth ground minus a voltage V
PL0
of the plate line PL
0
to the earth ground. A vertical axis indicates a polarization P of the ferroelectric capacitor
3
.
For example, when a logic “1” is written into the memory cell
1
, the voltage V
PL0
of the plate line PL
0
is set to 0 V, and the cell transistor
5
is set to be conductive. Under this condition, the voltage V
BL
of the bit line BL is changed from 0 V to VCC, and is subsequently changed to 0 V.
In the above sequence, a state of the polarization P of the ferroelectric capacitor
3
changes, as shown in
FIG. 2
, from a point a to a point b, and then to a point c. At the point c, the polarization P of the ferroelectric capacitor
3
becomes a positive polarization Ps. As a result, a logic “1” is stored in the ferroelectric capacitor
3
. A closed curved line of b to c to d to e to b indicates a hysteresis loop.
On the other hand, when a logic “0” is written into the memory cell
1
, the voltage V
BL
of the bit line BL is set to 0 V, and the cell transistor
5
is set conductive. Under this condition, the voltage V
PL0
of the plate line PL
0
is changed from 0 V to VCC, and is further changed to 0 V.
In the above sequence, a voltage of a storage electrode
3
A to that of a plate electrode
3
B of the ferroelectric capacitor
3
changes from 0 V to −VCC, and is further changed to 0 V. A state of the polarization P of the ferroelectric capacitor
3
changes, as shown in
FIG. 3
, from a point a to a point d, and then to a point e. At the point e, the polarization P of the ferroelectric capacitor
3
becomes a negative polarization −Ps. As a result, a logic “0” is stored in the ferroelectric capacitor
3
.
FIG. 4
shows waveforms for explaining a data-reading sequence from the memory cell of the ferroelectric memory. In the drawing, an example of the data-reading sequence from the memory cell
1
is shown. A waveform A indicates a variation of the voltage of the word lines WL
0
, DWL
0
, a waveform B indicates a variation of the voltage of the plate lines PL
0
, DPL
0
, and a waveform C indicates a variation of the voltage of the bit line BL.
FIG. 5
shows an illustration for explaining the data-reading sequence from the memory cell of the ferroelectric memory.
When data is read out from the memory cell
1
, the bit lines BL, /BL are set to 0 V, and the word lines WL
0
, DWL
0
are increased to VCC+VTH (a threshold voltage of the cell transistor) so as to set the cell transistors
5
,
11
conductive. Further, the plate lines PL
0
, DPL
0
are increased to VCC.
At this time, for example, when the logic “1” is previously written in the ferroelectric capacitor
3
, the polarization P of the ferroelectric capacitor
3
, as shown in
FIG. 5
, changes from a point c to a point K
1
. In this case, a charge &dgr;Q
1
, by which the voltage V
BL
of the bit line BL is the same as the voltage of the storage electrode
3
A of the ferroelectric capacitor
3
, is provided from the ferroelectric capacitor
3
to the bit line BL. As a result, the voltage V
BL
of the bit line BL increases from 0 V to V1 V as shown in FIG.
4
.
On the other hand, for example, when the logic “0” is previously written in the ferroelectric capacitor
3
, the polarization P of the ferroelectric capacitor
3
, as shown in
FIG. 5
, changes from a point e to a point K
2
. In this case, a charge &dgr;Q
2
, by which the voltage V
BL
of the bit line BL is the same as the voltage of the storage electrode
3
A of the ferroelectric capacitor
3
, is provided from the ferroelectric capacitor
3
to the bit line BL. As a result, the voltage V
BL
of the bit line BL increases from 0 V to V2 V shown in FIG.
4
.
Since the overlapped area of the opposite electrodes of the ferroelectric capacitor
9
in the dummy cell
7
is half that of the ferroelectric capacitor
3
in the memory cell
1
, and the logic “1” is written in the ferroelectric capacitor
9
in an initial condition, the voltage V
/BL
of the bit line /BL becomes an intermediate level between V1 and V2. This intermediate voltage may be the reference voltage (ope
Taira Shigenobu
Takai Kazuaki
Tamura Tetsuro
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fears Terrell W.
Fujitsu Limited
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