Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-06-13
2003-11-25
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000
Reexamination Certificate
active
06654274
ABSTRACT:
The present invention claims the benefit of Korean Patent Application No. P2001-38909 filed in Korea on Jun. 30, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, to a ferroelectric memory which can write data on a cell independent from amplification operation of a sense amplifier without restricted by the operation of the sense amplifier; and a method for driving the same.
2. Background of the Related Art
The ferroelectric memory, i.e., a Ferroelectric Random Access Memory (FRAM), having in general a data processing speed similar to a Dynamic Random Access Memory (DRAM), and being capable of conserving data even if the power is turned off, is paid attention as a next generation memory. The FRAM, a memory having a structure similar to the DRAM, is provided with a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of a data even after removal of an electric field.
FIG. 1
illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material.
Referring to
FIG. 1
, it can be known that a polarization induced by an electric field is, not erased totally, but, a certain amount(‘d’ or ‘a’ state) of which is remained, even if the electric field is removed owing to existence of the residual polarization(or spontaneous polarization). The ‘d’ and ‘a’ states are corresponded to ‘1’ and ‘0’ respectively in application to a memory.
A related art non-volatile ferroelectric memory will be explained with reference to the attached drawings.
FIG. 2
illustrates a unit cell of the related art non-volatile ferroelectric memory.
Referring to
FIG. 2
, the unit cell of the related art non-volatile ferroelectric memory is provided with a bitline B/L formed in one direction, a wordline W/L formed in perpendicular to the bitline, a plateline P/L formed spaced from the wordline in a direction identical to the wordline, a transistor T
1
having a gate connected to the wordline and a drain connected to the bitline, and a ferroelectric capacitor FC
1
having a first terminal connected to a source of the transistor T
1
and a second terminal connected to the plateline P/L.
The data input/output operation of the related art ferroelectric memory will be explained.
FIG. 3A
illustrates a timing diagram of a write mode operation of the related art ferroelectric memory, and
FIG. 3B
illustrates a timing diagram of a read mode operation of the related art ferroelectric memory.
In writing, when an external chip enable signal CSBpad transits from ‘high’ to ‘low’ and, on the same time, an external write enable signal WEBpad transits from ‘high’ to ‘low’, the write mode is started. When address decoding is started in the write mode, a pulse applied to the wordline transits from ‘low’ to ‘high’ to select the cell. Thus, in a period the wordline is held ‘high’, the plateline has a ‘high’ signal applied thereto for one interval and a ‘low’ signal applied thereto for the other interval in succession. And, in order to write a logical value ‘1’ or ‘0’ on the selected cell, a ‘high’ or ‘low’ signal synchronized to the write enable signal WEBpad is applied to the bitline. That is, if a ‘high’ signal is applied to the bitline, and a signal applied to the plateline is ‘low’ in a period in which a signal applied to the wordline is in a ‘high’ state, a logical value ‘1’ is written on the ferroelectric capacitor. If a ‘low’ signal is applied to the bitline, and a signal applied to the plateline is ‘high’, a logical value ‘0’ is written on the ferroelectric capacitor.
Then, the operation for reading the data stored in the cell will be explained.
If the chip enable signal CSBpad is transited from ‘high’ to ‘low’ from outside of the cell, all bitlines are equalized to a ‘low’ voltage by an equalizer signal before the wordline is selected. Then, after the bitlines are disabled, an address is decoded, and the decoded address transits the wordline from ‘low’ to ‘high’, to select the cell. A ‘high’ signal is applied to the plateline of the selected cell, to break a data corresponding to a logical value ‘1’ stored in the ferroelectric memory. If a logical value ‘0’ is in storage in the ferroelectric memory, a data corresponding to the logical value ‘0’ is not broken. The data not broken and the data broken thus provide values different from each other according to the aforementioned hysteresis loop, so that the sense amplifier senses a logical value ‘1’ or ‘0’. That is, the case of the data broken is a case when the value is changed from ‘d’ to ‘f’ in the hysteresis loop in
FIG. 1
, and the case of the data not broken is a case when the value is changed from ‘a’ to ‘f’ in the hysteresis loop in FIG.
1
. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case of the data broken, a logical value ‘1’ is provided as amplified, and in the case of the data not broken, a logical value ‘0’ is provided as amplified. After the sense amplifier amplifies data thus, since an original data should be restored, the plateline is disabled from ‘high’ to ‘low’ in a state a ‘high’ signal is applied to the wordline.
The following method may be used as one of methods for driving the related art ferroelectric memory.
A memory cell array is divided into a plurality of sub-cell arrays, and a selection switch signal SBSW is used. In a double pulse operation, a first pulse restores, or rewrites a cell data, a second pulse restores, or rewrites a logical “1”, i.e., a high data, broken by the first pulse, or to be written newly. In the meantime, an SBPD signal is used for reinforcing a logical “0”, i.e., a low data. That is, in the related art, after the operation of the sense amplifier is made by using the low data on the bitline, the low data is written again on the cell.
However, the aforementioned related art ferroelectric memory has the following problems.
The small design rule and cell size cause many difficulties in fabrication of the cell array and the peripherals, particularly, the use of poly related bitline which has a high resistance makes this problem more severe. High bitline resistance and bitline capacitance, when a ratio of Cb/CS (Cb: bitline capacitance, Cs: cell charge) is great, limits a cell size. In this case, a cell array efficiency is poor, resulting in a larger chip size. Moreover, in writing a low data, because the data is written again after the operation of the sense amplifier in which the low data on the bitline is used is finished, data writing can not be made during the operation of the sense amplifier, that increases a cell operation time period, and a cycle time period.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a ferroelectric memory and a method for driving the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a ferroelectric memory and a method for driving the same, which permits to write a data on a cell independent from an amplification operation of a sense amplifier without limited by the operation of the sense amplifier.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a ferroelectric memory device includes a cell array block having a plurality of sub-cell array blocks regularly arranged in columns and rows, each sub-cell array block includes a plurality of unit cells, a plurality of main b
Kang Hee Bok
Kim Duck Ju
Kye Hun Woo
Lee Geun Il
Park Je Hoon
Hynix / Semiconductor Inc.
Morgan & Lewis & Bockius, LLP
Phung Anh
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