Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-06-02
2001-10-09
Mai, Son (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C257S295000
Reexamination Certificate
active
06301145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory utilizing polarization inversion of ferroelectric substance and a method for accessing the same.
2. Description of the Related Art
Recently there has been active research into large capacity ferroelectric memories. A ferroelectric memory enables high speed access and is nonvolatile, so utilization for a main storage of a portable computer having a file storage and resume function and so on has been expected.
Initial attempts at using a ferroelectric capacitor to store data at a high density used a configuration called a simple matrix type which placed only a capacitor at an intersection of two orthogonal two drive lines (bit line and word line).
FIG. 1
is a circuit diagram of an example of the configuration of a simple matrix type ferroelectric memory.
This simple matrix type ferroelectric memory
1
is configured by a memory cell array
2
comprised of a plurality of (
20
in
FIG. 1
) ferroelectric capacitors FC
1
to FC
20
arranged in the form of a 4×5 matrix, a row decoder
3
, and a sense amplifier/column decoder
4
.
In the memory cell array
1
, one electrode each of the ferroelectric capacitors FC
1
to FC
5
, FC
6
to FC
10
, FC
11
to FC
15
, and FC
16
to FC
20
arranged in the identical row are connected to identical word lines WL
1
, WL
2
, WL
3
, and WL
4
, the other electrodes of FC
1
, FC
6
, FC
11
, and FC
16
arranged in the identical column are connected to a bit line BL
1
, the other electrodes of FC
2
, FC
7
, FC
12
, and FC
17
are connected to a bit line BL
2
, the other electrodes of FC
3
, FC
8
, FC
13
, and FC
18
are connected to a bit line BL
3
, the other electrodes of FC
4
, FC
9
, FC
14
, and FC
19
are connected to a bit line BL
4
, and the other electrodes of FC
5
, FC
10
, FC
15
, and FC
20
are connected to a bit line BL
5
.
Further, the word lines WL
1
to WL
4
are connected to the row decoder
3
, and the bit lines BL
1
to BL
5
are connected to the sense amplifier/column decoder
4
.
The ferroelectric capacitor has a hysteresis characteristic and stores and reads data by utilizing this hysteresis characteristic.
Below, an explanation will be made of the hysteresis characteristic of a ferroelectric capacitor In relation to
FIGS. 2A
to
2
C.
FIG. 2A
shows the hysteresis characteristic, while
FIGS. 2B and 2C
show states of the capacitor In which a first data (hereinafter referred to as a data “1”) and a second data (hereinafter referred to as a data “0”) having inverse phases to each other are written.
The ferroelectric memory is utilized as a nonvolatile memory by defining a state where a plus side voltage is supplied to a ferroelectric capacitor (C in
FIG. 2A
) and a residual polarization charge of +Qr remains (A in
FIG. 2A
) as the data “1” and defining a state where a minus side voltage is supplied (D in
FIG. 2A
) and a residual polarization charge of −Qr remains (B in
FIG. 2A
) as the data “0” in the hysteresis characteristic shown in FIG.
2
A.
Namely in the ferroelectriert memory, the polarizati o n of the ferroelectric film is used for the storage of the data and an electric field is added between the two electrodes configuring the capacitor for reading the data.
Where the field is given in an opposite direction to the polarization, the polarization state direction as that for the polarization, so the data can be read by detecting that difference.
For example, when reading the stored data of a memory cell MC
1
in
FIG. 1
, a predetermined potential difference is given between the bit line BL
1
and the word line WL
1
. By this, the charge stored in the ferroelectric capacitor FC
1
is released to the bit line BL
1
and the released charge is detected by the sense amplifier of the sense amplifier/column decoder
4
.
Summarizing the problem to be solved by the invention, in the case of this simple matrix type ferroelectric memory, since basically no transistor is required for a memory cell, an extremely small memory cell can be realized. In this configuration, however, there is the problem of disturbance as shown below.
For example, when writing the data “1” in the memory cell MC
1
(ferroelectric capacitor FC
1
), 0V is supplied to the word line WL
1
, and a power supply voltage V
cc
is supplied to the bit line BL
1
.
At this time, the potentials of for example the nonselected word lines WL
2
to WL
4
are fixed at V
cc
/2, but when for example the data “0” is written in the nonselected memory cell MC
2
(ferroelectric capacitor FC
6
), the ferroelectric capacitor FC
6
will receive a voltage of V
cc
/2, i.e., a so-called disturbance, in the direction in which the data is destroyed.
Accordingly, in a simple matrix type ferroelectric memory, the data of the capacitor for which the nonselection state contin ues for a long t ime gradually deteriorates and finally ends up disappearing. For this reason, the retention of the data could not be guaranteed and this memory was not suited for practical use.
Contrary to this, in U.S. Pat. No. 4,873,664, S. Sheffield et al. solved this problem by arranging a path transistor between the bit line and the capacitor electrode.
As the method for realizing this, a ferroelectric memory employing a method of configuring one memory cell by one path transistor and one ferroelectric capacitor to store one bit (one-transistor+one-capacitor type cell) is shown in FIG.
3
.
FIG. 3
is a circuit diagram of an example of the configuration of a folded bit line type ferroelectric memory having a one-transistor+one-capacitor type cell.
This ferroelectric memory
5
is configured by a memory cell array
6
comprising a plurality of (eight In
FIG. 3
) memory cells MC
01
to MC
08
arranged in the form of the matrix, a row decoder
7
. a plate decoder
8
, and sense amplifiers (S/A)
9
-
1
and
9
-
2
.
Each memory cell MC
01
(to MC
08
) is configured by one path transistor TR
01
(to TR
08
) and one ferroelectric capacitor FC
01
(to FC
08
).
Note that the path transistors TR
01
to TR
08
are configured by for example n-channel MOS transistors.
Further, one electrode each of the ferroelectric capacitors FC
01
and FC
03
configuring the memory cells MC
01
and MC
03
arranged in the identical column are connected via the path transistors TR
01
and TR
03
to a bit line BL
01
.
Similarly, one electrode each of the ferroelectric capacitors FC
02
and FC
04
configuring the memory cells MC
02
and MC
04
are connected via the path transistors TR
02
and TR
04
to a bit line BL
03
, one electrode each of the ferroelectric capacitors FC
05
and FC
07
configuring the memory cells MC
05
and MC
07
are connected via the path transistors TR
05
and TR
07
to a bit line BL
02
, and one electrode each of the ferroelectric capacitors FC
06
and FC
08
configuring the memory cells MC
06
and MC
08
are connected via the path transistors TR
06
and TR
08
to a bit line BL
04
.
Further, the other electrodes of the ferroelectric capacitors FC
01
and FC
02
configuring the memory cells MC
01
and MC
02
are connected to a common plate line PL
01
.
Similarly, the other electrodes of the ferroelectrio capacitors FC
03
to FC
06
configuring the memory cells MC
03
and MC
06
are connected to a common plate line PL
02
, and the other electrodes of the ferroelectric capacitors FC
07
and FC
08
configuring the memory cells MC
07
and MC
08
are connected to a common plate line PL
03
.
The gate electrodes of the path transistors TR
01
and TR
02
configuring the memory cells MC
01
and MC
02
arranged in the identical row are connected to a common word line WL
01
.
Similarly, the gate electrodes of the path transistors TR
03
and TR
04
configuring the memory cells MC
03
and MC
04
arranged in the identical row are connected to a common word line WL
02
, the gate electrodes of the path transistors TR
05
and TR
06
configuring the memory cells MC
05
and MC
06
arranged in the identical row are connected to a common word line WL
03
, and the gate electrodes of the path transistors TR
Kananen Ronald P.
Mai Son
Rader Fishman & Grauer
Sony Corporation
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