Ferroelectric memory and a test method thereof

Details Ferroelectric memory and a test method thereof Ferroelectric memory and a test method thereof

2002-07-12

2004-01-20

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S063000, C365S201000

Reexamination Certificate

active

06680861

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory, and particularly to a ferroelectric memory having a circuit structure for selecting a defective memory cell, and a method of efficiently selecting a defective memory cell lying within the ferroelectric memory with low power consumption.
This application is a counterpart of Japanese patent application, Serial Number 299875/2001, filed Sep. 28, 2001, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A FeRAM (Ferroelectric Random Access Memory) has been known as a conventional ferroelectric memory. For instance, a 2-transistor 2-capacitor/one-bit type is known as the FeRAM. The 2-transistor 2-capacitor/one-bit type FeRAM is a FeRAM which stores one binary information by means of two memory cells, i.e., two transistors and two capacitors.
As a reference that has disclosed the FeRAM, there is known, for example, “Low Power Consumption and High-Speed LSI Technology issued by Realize Co., Ltd, p.234-p.236”;
A memory cell array of a general FeRAM is provided with memory cell groups arranged in matrix form.
FIG. 12
shows a structure of such a memory cell array, corresponding to one sequence thereof. As shown in
FIG. 12
, a first memory cell M
0
and a second memory cell M
1
of a ferroelectric memory
2200
are respectively equipped with a first selection transistor T
0
, a second selection transistor T
1
, a first ferroelectric capacitor C
0
and a second ferroelectric capacitor C
1
. The first ferroelectric capacitor C
0
and the second ferroelectric capacitor C
1
respectively store binary data therein as polarization directions. In a 2-transistor 2-capacitor/1-bit type ferroelectric memory, binary or digitized data different in value are respectively stored in ferroelectric capacitors (e.g., the first ferroelectric capacitor C
0
and the second ferroelectric capacitor C
1
) of one memory cell pair (e.g., a pair of the first memory cell M
0
and the second memory cell M
1
).
FIG. 13
is a timing chart for describing a data read operation of the ferroelectric memory
2200
. In
FIG. 13
, ‘L’ indicates a ground voltage, and ‘H’ indicates a source voltage Vcc. Further, ‘Vh’ indicates a voltage which is higher than the source voltage Vcc and is increased by about a threshold voltage Vt of each of the first and second selection transistors T
0
and T
1
.
At a time t
1
, the voltage applied to a precharge control line PCHG is first rendered L to turn off a first precharge transistor PCT
0
and a second precharge transistor PCT
1
. Thus a first bit line BL
0
and a second bit line BL
1
are respectively brought to a floating state.
Next, the voltages applied to a first word line WL
0
and a second word line WL
1
are respectively set to the Vh to turn on the first selection transistor T
0
and the second selection transistor T
1
.
When the voltage applied to a first plate line PL
0
is brought to the H at a time t
3
, the voltage of the plate line PL
0
is applied to the first bit line BL
0
and the second bit line BL
1
through the first ferroelectric capacitor C
0
, the second ferroelectric capacitor C
1
, the first selection transistor T
0
and the second selection transistor T
1
, so that read voltages are developed in the first bit line BL
0
and the second bit line BL
1
. Since the first ferroelectric capacitor C
0
and the second ferroelectric capacitor C
1
are different in capacitance according to the direction of polarization, the read voltages developed in the first bit line BL
0
and the second bit line BL
1
are also different in value from each other according to the polarization direction.
When the voltage applied to an activation signal line SAE is brought to the H at a time t
4
, a sense amplifier SA is activated. Thus the voltages of the first bit line BL
0
and the second bit line BL
1
are amplified.
The voltage of the first plate line PL
0
is returned to the L at a time t
5
. Simultaneously, the voltage applied to a select line SEL is brought to the H. Consequently, a first bit line selection transistor SET
0
and a second bit line selection transistor SET
1
are turned on to output the read voltages of the first bit line BL
0
and the second bit line BL
1
onto a data bus
2210
.
The voltage applied to the precharge control line PCHG is brought to the H at a time t
6
, and the voltages applied to the activation signal line SAE and the select line SEL are respectively brought to the L. Thus the first precharge transistor PCT
0
and the second precharge transistor PCT
1
are turned on, so that the first bit line BL
0
and the second bit line BL
1
are grounded and the sense amplifier SA does not output read data.
Finally, the voltages applied to the first word line WL
0
and the second word line WL
1
are brought to the L at a time t
7
to turn off the first selection transistor T
0
and the second selection transistor T
1
.
FIG. 14
is a conceptual diagram for describing transition of state a ferroelectric capacitor. The horizontal axis indicates a voltage V [volt], and the vertical axis indicates polarization Pr [&mgr;C/cm
2
]. As shown in
FIG. 14
, the relationship between the voltage V and the polarization Pr plots or represents a hysteresis curve H. The inclination of the hysteresis curve H is equivalent to the capacitance [q/V] of the ferroelectric capacitor.
In
FIG. 14
, the coordinates of a point A where the hysteresis curve H and a Pr axis (region of Pr>0) intersect, is defined as (0, p0). A straight line S
1
is plotted which intersects, at an angle &thgr;, a straight line formed by connecting the point A (0, p0) and a point B (Vcc, p0). The coordinates of a point C where the straight line S
1
and an upward curve of the hysteresis curve H intersect, is defined as (v1, p1). The angle &thgr; is determined according to the capacitance of each bit line. The V coordinate v1 of the point C coincides with a terminal-to-terminal voltage of the ferroelectric capacitor, and the difference Vcc-v1 between the V coordinates of the points B and C coincides with a bit line voltage. Thus when Pr>0 (when a stored value is given as ‘0’), a voltage V
0
outputted onto the corresponding bit line is represented as Vcc-V
1
.
In
FIG. 14
, the coordinates of a point D where the hysteresis curve H and the Pr axis (region of Pr<0) intersect, is defined as (0, p2). A straight line S
2
is plotted which intersects, at the angle &thgr;, a straight line formed by connecting the point D (0, p2) and a point E (Vcc, p2). The coordinate of a point F where the straight line S
2
and an upward curve of the hysteresis curve H intersect, is defined as (v2, p3). Even in this case, the V coordinate v2 of the point F coincides with a terminal-to-terminal voltage of the ferroelectric capacitor, and the difference Vcc-v2 between the V coordinates of the points E and F coincides with a bit line voltage. Thus when Pr<0 (when a stored value is given as ‘1’), a voltage V
1
outputted onto the corresponding bit line is represented as Vcc-v2.
As is understood from
FIG. 14
, V
0
<V
1
, and the difference therebetween V
1
−V
0
results in a read margin &Dgr;V, V
0
, V
1
and &Dgr;V greatly depend on the angle &thgr;, i.e., bit line capacitance Cbl.
FIG. 15
is one example of a graph showing the relationship between a ratio Cbl/Cs between the capacitance Cbl of each bit line and capacitance Cs of the ferroelectric capacitor, and the read margin &Dgr;V. As is understood from
FIG. 15
, the read margin &Dgr;V can be maximized by adjusting the ratio Cbl/Cs. Increasing the read margin &Dgr;V makes it possible to improve the reliability of read data and enhance the yield of a FeRAM.
The capacitances Cbl of the first bit line B
10
and the second bit line BL
1
are made up of junction capacitances of the first selection transistor T
0
, the second selection transistor T
1
, the first precharge transistor PCT
0
and the second precharge transistor PCT
1
connected to the first bit line BL
0
and the s

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