Ferroelectric memory

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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Details

C365S210100

Reexamination Certificate

active

08085573

ABSTRACT:
A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel. The memory includes first and second memory cell arrays, first and second bit lines arranged in the first and second memory cell arrays, respectively, first and second blocks connected to the first bit line, and including N1units and N2units, respectively, where N1and N2are positive integers, third and fourth bit lines arranged in the first and second memory cell arrays, respectively, third and fourth blocks connected to the third bit line, and including N3units and N4units, respectively, where N3and N4are positive integers, first to fourth redundant blocks respectively connected to the first to fourth bit lines, and to be used for repair of the first to fourth blocks, and a sense amplifier selectively connectable to one of the first and second bit lines, and selectively connectable to one of the third and fourth bit lines.

REFERENCES:
patent: 5703817 (1997-12-01), Shiratake et al.
patent: 5959908 (1999-09-01), Shiratake
patent: 7791922 (2010-09-01), Doumae et al.
patent: 7830696 (2010-11-01), Shiratake
patent: 2004/0062134 (2004-04-01), Kato et al.
patent: 2004/0252542 (2004-12-01), Hoya et al.
patent: 2005/0063225 (2005-03-01), Takashima
patent: 2007/0047341 (2007-03-01), Domae et al.
patent: 2008/0186754 (2008-08-01), Shiratake
patent: 2010/0014341 (2010-01-01), Takashima
Explanation of Non-English Language References.

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