Ferroelectric memory

Details Ferroelectric memory Ferroelectric memory

2007-05-01

2007-05-01

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257SE29164, C257SE29172, C365S117000

Reexamination Certificate

active

11084150

ABSTRACT:
A ferroelectric memory comprises a first transistor connected between N1and N2nodes, a second transistor connected between the N2node and an N3node, a first transistor connected between P1and P2nodes, a second transistor connected between the P2node and a P3node, a first wiring formed in a first wiring layer to interconnect the N1node and the P1node, a second wiring formed in the first wiring layer to interconnect the N3node and the P3node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2node and the P2node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2node or the P2node.

REFERENCES:
patent: 5903492 (1999-05-01), Takashima
patent: 6091622 (2000-07-01), Kang
patent: 6094370 (2000-07-01), Takashima
patent: 6320782 (2001-11-01), Takashima
patent: 6657882 (2003-12-01), Takashima
patent: 6826072 (2004-11-01), Takashima
patent: 11-177036 (1999-07-01), None

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