Ferroelectric memory

Details Ferroelectric memory Ferroelectric memory

2006-02-14

2006-02-14

Mai, Son (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S063000, C365S069000

Reexamination Certificate

active

06999336

ABSTRACT:
A memory cell array includes ferroelectric memory cells arranged in m rows and n columns, bit lines provided along a row direction, and word lines and plate line provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between the fourth row and fifth row. The arrangement allows the connecting of four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells is reduced, to suppress deterioration of the ferroelectric memory cells. The word lines may instead intersect each other between the second and third lines, so that two ferroelectric memory cells are connected to the same plate and word lines.

REFERENCES:
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patent: 6504749 (2003-01-01), Jeon
patent: 6522567 (2003-02-01), Iwanari
patent: 6567329 (2003-05-01), Somasekhar et al.
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patent: 08-315584 (1996-11-01), None
patent: 2001-351373 (2001-12-01), None
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Masayuki Murakawa, “Low-power High-speed LSI Circuits & Technology”, Jan. 31, 1998, pp. 231-249.
Japanese Patent Kokai No. 2002-15563 “Low-power High-speed LSI Circuits & Technology” p. 231-247.

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