Ferroelectric memory

Details Ferroelectric memory Ferroelectric memory

2005-03-22

2005-03-22

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S063000, C365S069000, C365S149000

Reexamination Certificate

active

06870754

ABSTRACT:
A memory cell array includes ferroelectric memory cells arranged in the form of m rows and n columns, bit lines provided along a row direction, and word lines and plate lines provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between the fourth row and the fifth row. The arrangement allows the connecting of four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half of the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells can be reduced, thereby deterioration of the ferroelectric memory cells can be suppressed.

REFERENCES:
patent: 6363003 (2002-03-01), Miyamoto
patent: 6504749 (2003-01-01), Jeon
patent: 6522567 (2003-02-01), Iwanari
patent: 08-315584 (1996-11-01), None
patent: 2001-351373 (2001-12-01), None
patent: 2002-015562 (2002-01-01), None
Japanese Patent Kokai No. 2002-15562, “Low-power High-speed LSI Circuits & Technology” p. 231-247.
Masayuki Murakawa,“Low-power High-speed LSI Circuits & Technology”, Jan. 31, 1998, pp. 231-249. (English translation included).

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