Ferroelectric memory

Details Ferroelectric memory Ferroelectric memory

2001-07-25

2002-04-16

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S200000, C365S189090

Reexamination Certificate

active

06373744

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory and concerns a nonvolatile ferroelectric memory for storing data by using characteristics of a ferroelectric capacitor.
BACKGROUND OF THE INVENTION
In recent years, of nonvolatile memories, a nonvolatile ferroelectric memory has become a focus of attention. The nonvolatile ferroelectric memory stores data by using characteristics of a ferroelectric capacitor, dramatically improves the number of times of rewriting as compared with a flash memory and an EEPROM, and increases a reading speed and a writing speed with a low source voltage.
First, the following will briefly describe operations of the ferroelectric memory having the above characteristics.
FIG. 10
is a circuit block diagram showing a configuration of a conventional ferroelectric memory. As shown in
FIG. 10
, the ferroelectric memory is constituted by a memory M
10
including a memory cell MC
10
and a precharge circuit PC
10
, and a memory control section MS
10
for controlling the memory cell MC
10
and the precharge circuit PC
10
. The memory cell MC
10
has a
2
T (transistor)/
2
C (capacitor) configuration.
FIG. 11
is a timing chart showing control signals in the memory control section MS
10
of the ferroelectric memory shown in FIG.
10
.
In
FIGS. 10 and 11
, reference character XEXTCE denotes an external input control signal, reference character INTCE denotes an internal circuit control signal, reference character WL denotes a word line, reference characters BL and /BL denote bit lines, reference character CP denotes a cell plate electrode, reference character BP denotes a bit line precharge control signal, reference character SAE denotes a sense amplifier control signal, reference character VSS denotes a ground voltage, reference character SA denotes a sense amplifier, reference numerals CM
0
and CM
0
B denote memory cell capacitors using a ferroelectric material, reference numerals QnWL
1
, QnWL
2
, and QnBP
0
to QnBP
2
denote N-channel MOS transistors, reference numeral
100
denotes a CE initial-stage circuit for producing the internal circuit control signal INTCE from the external input control signal XEXTCE, and reference numeral
101
denotes a control circuit for producing signals WL, CP, BP, and SAE from the internal circuit control signal INTCE.
The bit lines BL and /BL are connected to the sense amplifier SA, and the sense amplifier SA is controlled by the sense amplifier control signal SAE.
The first electrode of the memory cell capacitor CM
0
is connected to the bit line BL via the memory cell transistor QnWL
1
whose gate electrode is connected to the word line WL.
The second electrode of the memory cell capacitor CM
0
is connected the cell plate electrode CP. The first electrode of the memory cell capacitor CM
0
B, which is paired with the memory cell capacitor CM
0
, is connected to the bit line /BL via the memory cell transistor QnWL
2
whose gate electrode is connected to the word line WL. The second electrode of the memory cell CM
0
B is connected to the cell plate electrode CP.
Further, the bit lines BL and /BL are connected to each other via the N-channel MOS transistor QnBP
0
. The bit line BL and the ground voltage VSS, and the bit line /BL and the ground voltage VSS are respectively connected to the N-channel MOS transistors QnBP
1
and QnBP
2
. The gate electrodes of the N-channel MOS transistors QnBP
0
to QnBP
2
are controlled by the bit line precharge control signal BP.
The memory cell capacitors CM
0
and CM
0
B store a logical state (“1” or “0”) of data depending upon an electrical polarization state of ferroelectric capacitors constituting the memory cell capacitors CM
0
and CM
0
B. When a voltage is applied between the electrodes of the memory cell capacitors CM
0
and CM
0
B, the ferroelectric material is polarized in a direction of an electric field.
Referring to
FIG. 11
, the following will briefly discuss the reading operation of the ferrorelectric memory configured thus.
FIG. 11
is a timing chart showing the control signals for exercising memory control in the conventional ferroelectric memory. As shown in
FIG. 11
, in an initial state, the external input control signal XEXTCE activated at logical voltage “L” is at logical voltage “H”, the internal circuit control signal INTCE is at logical voltage “L”, the bit line precharge control signal BP is at logical voltage “H”, and the bit lines BL and /BL are at logical voltage “L”. Moreover, the word line WL, the cell plate electrode CP, and the sense amplifier control signal SAE are at the ground voltage VSS, which is at logical voltage “L”.
Firstly (at timing of time T
1
), since the external input control signal XEXTCE is set at logical voltage “L”, the internal circuit control signal INTCE is changed to logical voltage “H” and the bit line precharge control signal BP is changed to logical voltage “L”. Hence, the bit lines BL and /BL are brought into a floating state.
Next, at timing of time T
2
, the word line WL and the cell plate electrode CP are set at logical voltage “H”, and data of the memory cell capacitors CM
0
and CM
0
B is read to the bit lines BL and /BL.
And then, at timing of time T
3
, the sense amplifier control signal SAE is set at logical voltage “H”, data is amplified, the reading operation is started, and data of the memory cell capacitors CM
0
and CM
0
B is rewritten in two states of logical voltage “H” of the cell plate electrode CP after the amplification of data and logical voltage “L” of the cell plate electrode CP.
Next, at timing of time T
4
, since the sense amplifier control signal SAE is set at logical voltage “L”, the operation of the sense amplifier SA is suspended. And then, at timing of time T
5
, since the bit line precharge control signal BP is set at logical voltage “H”, the bit lines BL and /BL return to a logical voltage “L” and a potential across the memory cell is made equal.
Subsequently, at timing of time T
6
, the word line WL is set at logical voltage “L”, the bit lines BL and /BL and the memory cell are made unconnected with each other and are brought into the initial state.
As described above, in addition to during the writing operation, the ferroelectric memory performs rewriting during and after the reading operation. Further, as compared with a flash memory demanding a high voltage for rewriting data, just because of a difference in potential across the memory cell capacitor, charge is transferred and the rewriting operation is carried out. Thus, it is quite important to protect data from a malfunction even at a low voltage.
Considering the operations when the power is turned on and off on a ferrorelectric memory section (memory section M
10
of
FIG. 10
) and a logical section (memory control section MS
10
of
FIG. 10
) including a microcomputer for controlling the memory section, control signals produced from the microcomputer (logic) section may be undefined. In this case as well, data needs to be protected.
Moreover, considering the timing of suspending the operation, the operation of the microcomputer (logic) section can be immediately suspended without any problems. However, regarding the ferroelectric memory requiring rewriting after reading, data needs protection during the operation.
Therefore, even at a voltage other than a guaranteed source voltage, particularly at a low voltage when the power is turned on and off, it is not possible to maintain nonvolatile characteristics unless data is protected by exercising control for avoiding a reading operation and a writing operation based on the relationship between a source voltage and a potential of an external control signal.
Hence, regarding the ferroelectric memory, the presence of a circuit, which detects a source voltage value, prevents a malfunction in response to a detection signal, and protects stored data, is more important than a conventional nonvolatile memory. A source voltage detection circuit configured as below is required as a circuit capable of operating thus.
Referring to
FIG. 12
, the following will discuss a

Affiliated with

Also associated with

Rating

Ferroelectric memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ferroelectric memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2883399