Ferroelectric memory

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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Details

C365S189090

Reexamination Certificate

active

07319607

ABSTRACT:
A ferroelectric memory, upon reading of a memory cell array, in which the plate line PL is charged to the power supply potential VDD by a driving control circuit prior to driving of the relevant word line WL. The bit lines BL and /BL are charged to the potential VDD by a timing control circuit, then the word line WL is driven. At this time, the lines BL and /BL are discharged by applying an equalizing signal EQ with predetermined pulse width to a reset circuit.

REFERENCES:
patent: 5619470 (1997-04-01), Fukumoto
patent: 5963467 (1999-10-01), Miyatake et al.
patent: 6965520 (2005-11-01), Seshadri et al.
patent: 7064972 (2006-06-01), Takashima
patent: 05-114741 (1993-05-01), None
patent: 06-223583 (1994-08-01), None
patent: 07-111085 (1995-04-01), None
patent: 2000-076870 (2000-03-01), None
patent: 3110032 (2000-09-01), None

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