Ferroelectric capacitor with a self-aligned diffusion barrier

Details Ferroelectric capacitor with a self-aligned diffusion barrier Ferroelectric capacitor with a self-aligned diffusion barrier

2000-10-31

2002-04-30

Lebentritt, Michael S. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S310000, C365S065000, C438S003000

Reexamination Certificate

active

06380574

ABSTRACT:

TECHNICAL FIELD
This invention concerns a device using a ferroelectric thin film and, more in particular, it relates to a capacitor for polarization reversion type non-volatile memories or dynamic random access memories suitable to large scale integrated circuits (LSI).
BACKGROUND ART
Ferroelectric materials include those having a specific permittivity as high as from several hundreds to several thousands. Accordingly, when a thin film of such ferroelectric material is used for a capacitor insulation film, a capacitor of a small area and a large capacity suitable to large scale integrated circuits (LSI) can be obtained. Further, since the ferroelectric material has spontaneous polarization and the direction thereof can be reversed by external electric fields, a non-volatile memory can be obtained by utilizing such characteristic. As ferroelectric thin films in the memory using ferroelectric material, oxide ferroelectrics such as lead zirconate titanate and strontium barium titanate are generally used.
While the ferroelectric material has high dielectric permittivity, charges required for obtaining sufficient reliability can not be stored in a plane capacitor, for example, in 1 Gbit DRAM even when a capacitor dielectric film with the dielectric permittivity of 250 is used , so that a three-dimensional capacitor structure is necessary. Trial manufacture for 1 Gbit DRAM has been reported, for example, in I.E.E.E., I.E.D.M. Technology Digest 1995, p 119 (IEDM' 95 Tech, Digest pp 119, 1995) or I.E.E.E., I.E.D.M. Technology Digest 1995, p 115 (IEDM' 95 Tech, Digest pp 115, 1995). Memory cells used in the prior art described above have a structure as shown in
FIG. 20. A
semiconductor substrate formed with a switching MOS transistor including a gate oxide film
202
and a gate electrode
203
is covered with an interlayer insulation film
206
and, after flattening an underlying step, a diffusion barrier layer
207
is formed thereon to form a dielectric capacitor of high dielectric permittivity comprising a lower electrode
208
, a high permittivity dielectric film
209
and a plate electrode
210
. Platinum, ruthenium, ruthenium dioxide or the like is used for the lower electrode
208
. In this structure, connection with one electrode
208
of the ferroelectric capacitor and the source or drain of the MOS transistor is conducted with conductive material
205
buried in a contact hole perforated in an insulation material. In the drawing,
204
denotes a bit line and
201
denotes an inter-device isolation film. As described above, by forming the lower electrode as a cuboid electrode and utilizing the lateral sides thereof, a capacitor having a large area in one identical plane area can be attained.
However, the existent structure as shown in
FIG. 20
involves a problem that a lateral side
211
of the diffusion barrier layer
207
is oxidized and peeled during the preparation of a high dielectric permittivity dielectric material
209
. Further, when a mask defining the bottom of the memory contact and the storage capacitor are misaligned, this may possibly cause a problem that a memory contact plug
205
and the capacitor insulation film
209
are brought into a direct contact in which the memory contact plug is oxidized to cause conduction failure due to an oxidizing atmosphere upon preparing the high permittivity dielectric film
99
, or the memory contact plug is scraped upon fabricating the lower electrode.
To fabricate higher density memories with the existent structure, since it is necessary to further enlarge the lateral area for ensuring the capacitance of a capacitor, it is required to make this cuboid lower electrode
207
finer and higher. For example, considering DRAM of a minimum fabrication size of 0.13 &mgr;m, it is expected that fabrication to make the aspect ratio of the cuboid to 3-5 will be necessary. However, ultra fine fabrication technique of such material has not been well established and, particularly, ultra fine patterning with the high aspect ratio is difficult. Further, for increasing the height of the electrode, it is at first necessary to deposit the material for the lower electrode such as ruthenium dioxide by so much as the thickness for the required height. However, as the film thickness increases, it results in a problem of taking long deposition time or tending to cause peeling by the stress of the film itself, to lower the yield.
On the other hand, it has been proposed a structure of forming a diffusion barrier layer only in the contact hole or using TiN, W for the contact plug. However, even when such method is used, problems such as oxidation of the diffusion barrier layer and scraping of the lower electrode upon fabrication can not be avoided.
For avoiding the problem in the prior art, as shown in
FIG. 25
, JP-A No. Hei 5-291526 proposes a structure of forming a lower electrode
81
into a thin wall shape in the inside of a cylindrical hole opened to a thick insulation film. However, application of this structure to a high dielectric permittivity dielectric capacitor results in the following problem. That is, in the high dielectric permittivity dielectric capacitor, material such as platinum, ruthenium or ruthenium dioxide is used for the lower electrode. However, when one of the diffusion layers of the switching MOS transistor and the lower electrode of the capacitor are connected, silicidation reaction occurs if the material is in direct contact with silicon
53
, or silicon is oxidized at the electrode/silicon interface to increase resistance. Accordingly, it is necessary to dispose a diffusion barrier layer between the electrode
81
and the silicon
53
. If the diffusion barrier layer and the lower electrode bottom face are misaligned, a side trench
261
is formed as shown in
FIG. 26
due to the difference of the etching rate between the underlying interlayer insulation film and the diffusion barrier layer when a hole as a capacitor region is opened to the thick insulation film, to deteriorate the reliability.
This invention has been achieved in order to overcome the foregoing problems and it intends to provide a semiconductor device capable of attaining a higher density memory, as well as a method for manufacturing the same.
DISCLOSURE OF THE INVENTION
Means for Dissolution
The object described above can be attained by depositing a diffusion barrier layer, then forming a second film for defining a capacitor region, etching the second film and the diffusion barrier layer selectively to conduct patterning, fabricating the same into an island pattern of a capacitor region, then forming a thick insulation film thereby burying the island pattern into the thick insulation film and then removing the second film buried in the insulation film thereby forming the bottom of the hole as the capacitor region and the diffusion barrier layer.
Further, the object can be attained by providing a diffusion barrier layer disposed to the bottom of a hole of an insulation film on a substrate formed with a transistor and a lower electrode of a capacitor formed in self alignment with the underlying diffusion barrier layer from the bottom to the lateral side of the hole. The lower electrode and the diffusion barrier layer are formed in a substantially identical pattern.
With the constitution described above, since the side wall of the hole as the capacitor region is used for the capacitance of the capacitor, a capacitor of a large capacitance suitable for high density memories can be obtained. Further, since the diffusion barrier layer is formed in self alignment at the bottom of the hole as the capacitor region, side trench upon forming the hole as the capacitor region can be prevented without increasing the memory cell area. Further, even when the storage node contact plug and the diffusion barrier layer are misaligned, the contact plug and the high dielectric permittivity dielectric film are not in direct contact with each other to obtain a device of high reliability.
The diffusion barrier layer is a layer for preventing reaction between the low

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