Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-12-21
2003-06-10
Wille, Douglas A (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S429000
Reexamination Certificate
active
06576922
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to the art of semiconductor devices and more particularly to methods and apparatus for monitoring plasma charging during semiconductor processing.
BACKGROUND OF THE INVENTION
In the course of manufacturing semiconductor devices, certain processing steps involve the use of electrically charged plasma. Ion implantation, plasma etching, and other charged processing steps may damage semiconductor wafers, and the devices and circuits thereof. For instance, plasma dry etching operations employ an electrically excited gas etchant, where the surface to be etched is coated with a patterned layer of photoresist and then exposed to a gaseous plasma of the gas. Plasma dry etching is often used for controlled etching of high density features and is generally anisotropic, whereas wet etching techniques are commonly used to remove large volumes of material, being generally isotropic. Despite having certain advantages in many applications where anisotropic etching is desired, plasma etching can cause charge accumulation in semiconductor wafer workpieces being etched. The plasma is made up of a mix of charged particles, and there is a tendency for some such charged particles to accumulate on the wafer surface through what is sometimes referred to as the antenna effect.
This charge accumulation can lead to damage of transistors, gates, circuits, and other structures in the finished product. For example, plasma related charging can result where there are large antennas of conducting material such as metal or polysilicon in the workpiece, which may be electrically connected to transistor gates with thin gate oxide. Such antennas may collect a relatively high level of electrical charge by virtue of their large areas during plasma based processing operations. The collected charge may then be conducted through circuit paths in the wafer due to a voltage potential developed between the wafer surface and the underlying substrate material. This charge may thus be conducted to transistors or other devices in the wafer, resulting in performance degradation and/or damage thereto.
Various devices have thusfar been developed to measure the resulting voltage potential (or a current flow) between a charge collection area on the surface of the semiconductor device wafer and the substrate of the semiconductor wafer. Such devices include monitors or sensors located proximate the wafer workpieces during implantation or other processing steps involving plasma, which provide sensor signals to control systems or user interface devices. The actual charging of the semiconductor wafer is then inferred from the sensor signal. Other plasma charging measurement devices have been developed, which are formed directly in the wafer workpieces or in dedicated test wafers. These in-situ plasma charging sensors typically consist of dedicated memory cells, such as one or more electrically erasable programmable read only memory (EEPROM) cells formed in the wafer. For example, one or more such EEPROM memory cells may be provided, having a stacked gate MOS type transistor operating as voltage or current sensor.
In such memory type detector devices, a charge collection electrode is located on the top of the wafer, and is associated with the control gate of a stacked gate MOS type transistor, so as to collect plasma related charge during processing, which in turn affects the transistor gate. As plasma related charge is collected at the wafer surface, the transistor based memory cell measures the resulting voltage potential between the charge collection electrode and the wafer substrate. The voltage potential in the wafer, in turn changes the threshold voltage Vt of the memory cell, and hence the threshold voltage Vt thereof can be measured before and after a plasma related processing step. A comparison of the threshold voltage measurements is then used to estimate the plasma charging associated with the processing step. For instance, the threshold voltage shift of the sensing transistor may be used to calculate the plasma charging voltage during plasma processing.
More than one such charge monitoring devices are typically provided to monitor the wafer during fabrication and processing. A first or initial threshold voltage is programmed prior to exposing the wafer to a plasma related process, typically by probing the wafer and providing a known programming signal to the transistor via the charge collection electrode. At this point, the actual initial threshold voltage is sometimes measured or verified, prior to performing wafer processing steps involving plasma. After the processing step or steps of interest, the EEPROM transistor is probed and a second or final threshold voltage is measured. Once the initial and final threshold voltages are determined, then the surface potential related to the plasma can be estimated using a calibration curve or plot of threshold voltage shift versus gate voltage for the EEPROM transistor. In this regard, the estimated gate voltage represents the voltage potential between the charge collection electrode at the wafer surface and the wafer substrate. Where a resistance of known value is provided between the charge collection electrode and the substrate, then the plasma processing related current can be determined according to the gate voltage and the known resistance value. In this fashion, EEPROM transistor-based charge detection devices can be used to estimate the plasma related charging of a particular processing step.
However, these devices suffer from several shortcomings. For example, EEPROM memory cell type charging sensors are limited to detecting voltage, for example, in a range of about −25 to +30 volts. Consequently, these EEPROM type monitor devices are unable to quantify or measure plasma related potentials above this range. Furthermore, the threshold voltage of the EEPROM cell type detectors is sensitive to ultra-violet (UV) radiation. As a result, the threshold voltage shift represents both plasma process related charging and exposure of the wafer to UV sources during processing. Thus, it may be difficult or impossible to differentiate between the two in order to accurately quantify the plasma charging in the manufacturing process. Moreover, the construction of EEPROM memory cells is relatively complex, requiring the formation in the wafer of the source, drain, and gate structures of the MOS type transistor, thereby making the manufacturing process more difficult. Thus, there is a need for improved plasma charging monitor devices and methodologies by which plasma charging effects in semiconductor device manufacturing processes can be characterized, without the UV sensitivity and voltage range limitations associated with prior insitu and other charging sensors.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention relates to apparatus and methods for monitoring plasma related charging in a semiconductor wafer, by which the above mentioned and other shortcomings associated with the prior art may be mitigated or avoided. Ferroelectric (FE) capacitor plasma charging monitor devices are provided, which are relatively simple to design and fabricate in production and/or test wafers, and which do not suffer from the UV sensitivity problems associated with EEPROM type insitu monitors. In addition, the FE sensor devices are not limited by the voltage detection ranges achievable in prior transistor-based memory cell charging sensors. The invention can thus be employed to quantify plasma processing related charging effects associated with process steps, including for examp
Gilbert Stephen R.
Ma Shawming
Xing Guoqiang
Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Wille Douglas A
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