Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-17
2003-11-18
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06649954
ABSTRACT:
BACKGROUND OF THE INVENTION
A) Field of the Invention
This invention concerns a non-volatile semiconductor memory, a ferroelectric capacitor, and a ferroelectric capacitor manufacturing method, and in particular, concerns a non-volatile semiconductor memory with a ferroelectric capacitor, a ferroelectric capacitor with a laminated upper electrode, and a ferroelectric capacitor manufacturing method that makes use of sputtering.
B) Description of the Related Art
A ferroelectric random access memory (FeRAM) is a memory, which uses a ferroelectric capacitor that has a capacitor dielectric layer formed from a ferroelectric, is made non-volatile by the retention of polarization, and is made rewritable by the inversion of polarization.
Examples of the ferroelectric used include Pb(Zr, Ti)O
3
(PZT), (Ba, Sr)TiO
3
(BST), Bi
4-x
La
x
Ti
3
O
12
(BLT), SrBi2Ta
2
O
9
(SBT), etc. Here, the expression (A, B) indicates Ah
x
B
1-x
.
PZT, Pb
1-a
La
a
Zr
x
Ti
1-x
Ti
1-x
O
3
(PLZT), Pb
1-a-b-c
La
a
Sr
b
Ca
c
Zr
x
Ti
1-x
O
3
(PLSCZT), etc., are ferroelectrics with perovskite crystal structures. In this Specification, these shall be referred to collectively as PZT ferroelectrics or PZT materials.
For the lower electrode and upper electrode that sandwich the ferroelectric layer, Pt, Ir, Ru, SrRuO
x
(SRO, though the stoichiometric composition is SrRuO
3
, the expression, SrRuO
x
shall be used to include cases where the composition is not strictly stoichiometric), LaNiO
3
(LNO), (La, Sr)CoO
3
(LSCO), etc., which are strong in resistance against reducing atmospheres containing H
2
, are used. Among these, SRO, LNO and LSCO have perovskite crystal structures.
As with other devices, a higher degree of integration, increased speed, and lower power supply voltage are being demanded for FeRAM's as well. It is being desired that the power supply voltage be less than 3V. With an FeRAM that uses PZT for the ferroelectric layer of the ferroelectric capacitor, the thickness of the ferroelectric layer must be made no more than 100 nm in order to decrease the power supply voltage.
As the layer thickness of a ferroelectric layer is decreased, the minimum electric field (coercive field Ec) necessary for inverting the polarization of the ferroelectric capacitor increases, especially when metal electrodes are used. It is considered that the coercive field increases due to increased contribution of the interface with a decrease in the ferroelectric layer thickness. It is desired that excellent contact be formed and the occurrence of interfacial stress be avoided.
Priorly, Pt electrodes were often used as the electrodes of a PZT ferroelectric capacitor. Pt exhibits a catalytic action and has the function of decomposing hydrogen into protons. When protons are generated, the protons diffuse into the PZT layer and degrade the ferroelectricity. However, even in the case where Pt electrodes are used, the catalytic action can be reduced significantly by covering the Pt layer with another layer.
As with PZT, SRO has a perovskite structure. The use of SRO as an upper electrode is effective for excellent contact formation and reduction of distortion. Among the raw materials for SRO, Ru is an expensive raw material. Thus for the reduction of manufacturing cost, it is desired that the consumption of Ru be decreased.
In the case where an SRO target for sputtering is to be formed from sintered ceramic, it is difficult to increase the density of the SRO target. The density of an ordinary ceramic SRO target is approximately 65% at the most. A low density target not only causes the lifetime to be short but also causes particle generation.
Sr also has a low rate of etching by chlorine or other halogen etching gas, and it is therefore not easy to etch SRO chemically.
For ferroelectric capacitors that use a ferroelectric layer, electrodes that can form an excellent interface with the ferroelectric layer are needed.
The making of the lifetime of the SRO target long and the reduction of the cost of manufacture are also required.
SUMMARY OF THE INVENTION
An object of this invention is to provide a non-volatile semiconductor memory and a ferroelectric capacitor, which has excellent performance and can be manufactured efficiently.
Another object of this invention is to provide a method of manufacturing a ferroelectric capacitor and a non-volatile semiconductor memory by which a ferroelectric capacitor with excellent characteristics can be manufactured efficiently.
A further object of this invention is to provide a new art regarding a ferroelectric capacitor and a non-volatile semiconductor memory.
An aspect of this invention provides a non-volatile semiconductor memory comprising a base substrate having an insulating surface; a lower electrode formed on said insulating surface; an oxide ferroelectric layer formed on said lower electrode, a first oxide upper electrode formed on and in contact with an upper surface of said oxide ferroelectric layer; and a second oxide upper electrode formed on said first oxide upper electrode, wherein one of said first and second oxide upper electrodes comprises SRO that contains at least 0.1 at % additive and other of said first and second oxide upper electrodes comprises IrO
x
.
Another aspect of this invention provides a ferroelectric capacitor manufacturing method comprising the steps of (a) forming a lower electrode on a base substrate having an insulating surface;(b) forming an oxide ferroelectric layer on said lower electrode; and (c) depositing a first and a second oxide upper electrodes onto said oxide ferroelectric layer by sputtering wherein one of said first and second oxide upper electrodes is sputtered using a target that comprises SRO ceramic that has an increased density by adding at least 0.1 at % additive and the other of said first and second oxide upper electrodes is sputtered using a target comprising of Ir.
A further aspect of this invention provides a ferroelectric capacitor, comprising a base substrate having an insulating surface; a lower electrode formed on said insulating surface; an oxide ferroelectric layer formed on said lower electrode, a first oxide upper electrode formed on and in contact with an upper surface of said oxide ferroelectric layer; and a second oxide upper electrode formed on said first oxide upper electrode, wherein one of said first and second oxide upper electrodes comprises CaRuO
x
or LaRuO
x
that contains at least 0.1 at % additive and other of said first and second oxide upper electrodes comprises IrO
x
.
A non-volatile semiconductor with excellent characteristics can thus be manufactured efficiently. Since an SRO layer is sputtered, the lifetime of the target can be increased. The cost of manufacture of the ferroelectric capacitor can also be reduced.
REFERENCES:
patent: 5293075 (1994-03-01), Onishi et al.
patent: 41114541 (1999-05-01), None
patent: 11-195768 (1999-07-01), None
patent: 2000-156471 (2000-06-01), None
patent: 2000-208725 (2000-07-01), None
patent: 2000-260954 (2000-08-01), None
patent: 2000-349246 (2000-12-01), None
patent: 3171110 (2001-03-01), None
patent: 2001-144067 (2001-05-01), None
patent: 2001-144264 (2001-05-01), None
patent: 2001-196547 (2001-07-01), None
LandOfFree
Ferroelectric capacitor having upper electrode lamination does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ferroelectric capacitor having upper electrode lamination, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric capacitor having upper electrode lamination will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3126307