Ferroelectric capacitor having a PZT layer with an excess of Pb

Details Ferroelectric capacitor having a PZT layer with an excess of Pb Ferroelectric capacitor having a PZT layer with an excess of Pb

2000-02-29

2003-04-29

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S532000

Reexamination Certificate

active

06555864

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority application No.11-57601 filed on Mar. 4, 1999, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to the fabrication process of a semiconductor memory device having a ferroelectric film.
Semiconductor memory devices such as DRAMs or SRAMs are used extensively in various information processing apparatuses including computers as a high-speed main memory. On the other hand, DRAMs or SRAMs are volatile in nature and the information held therein is lost when the electric power is turned off. Thus, in order to store programs or data, conventional computers or other information processing apparatuses have used a magnetic disk device as a large-capacity, non-volatile storage device.
A magnetic disk device, however, has a drawback in that it is bulky and mechanically fragile. Further, there are additional drawbacks such as large power consumption and slow access speed.
In view of the foregoing various drawbacks of magnetic disk devices, there is a proposal to use a semiconductor non-volatile memory device such as EEPROM or flash memory as the non-volatile storage device of computers. An EEPROM or a flash memory has a floating gate electrode and stores information in the floating gate electrode in the form of electric charges. Particularly, a flash-memory has a cell structure similar to that of a DRAM and is suitable for use in constructing a large-scale integrated circuit.
Meanwhile, such EEPROM or flash memory has a drawback in that it takes time to write information into the memory device, as the writing of information is achieved by injection of hot electrons into the floating gate electrode through a tunneling insulation film. Further, there arises a problem that the tunneling insulation film becomes deteriorated when reading or writing of information is conducted repeatedly. When the tunneling insulation film has become deteriorated, writing or erasing of information becomes unreliable.
On the other hand, there is a different type of semiconductor non-volatile memory device called ferroelectric semiconductor memory (FeRAM), in which information is stored in a ferroelectric film in the form of spontaneous polarization. An FeRAM includes a single MOSFET as a memory cell transistor and a memory cell capacitor similar to a conventional DRAM, except that the dielectric film in the memory cell capacitor is replaced with a ferroelectric film such as PZT (Pb(Zr,Ti)O
3
), PLZT(Pb(Zr,Ti,La)O
3
), BST ((Ba,Sr)TiO
3
) or SBT(SrBi
2
Ta
2
O
3
). Thus, an FeRAM has a structure suitable for constructing a large-scale integrated circuit with a high integration density.
As noted above, writing of information is achieved in an FeRAM by controlling the spontaneous polarization of the ferroelectric capacitor, wherein the control of the spontaneous polarization is achieved by applying an electric field to the ferroelectric film constituting the ferroelectric capacitor. Thus, an FeRAM has an inherently high operational speed, which is faster than an EEPROM or a flash memory, in which writing is achieved by injection of hot-electrons, by a factor of 1,000 or more. Further, the electric power consumption is reduced by a factor of about {fraction (1/10)} in an FeRAM. Furthermore, an FeRAM, not using a tunneling insulation film, has an advantageous feature of long life-time, longer than a flash memory by a factor of 10,000.
FIG. 1
shows the construction of a conventional FeRAM.
Referring to
FIG. 1
, an FeRAM
10
is constructed on a p-type Si substrate
11
, on which an active region is defined by a field oxide film
12
. The active region is covered by a gate oxide film not designated in
FIG.1
by a reference numeral, and a gate electrode
13
is provided on the gate oxide film in corresponding to a word line of the FeRAM. Further, diffusion regions
11
A and
11
B of the n
+
-type are formed in the substrate
11
at both lateral sides of the gate electrode
13
as source and drain regions of the memory cell transistor. In the substrate
11
, a channel region is formed between the foregoing diffusion regions
11
A and
11
B.
It should be noted that the gate electrode
13
is covered by a CVD-oxide film
14
deposited on the substrate
11
so as to cover the active region, and the CVD-oxide film
14
in turn is covered by a planarizing interlayer insulation film
15
. The interlayer insulation film
15
is formed with a contact hole
15
A exposing the diffusion region
11
B, and a WSi plug
16
is formed such that the WSi plug
16
fills the contact hole
15
A.
Further, an adhesion layer of Ti/TiN structure (not shown) is formed on the interlayer insulation film
15
including the part where the plug
16
is exposed, and a lower electrode
17
of Pt, and the like, is formed on the adhesion layer thus formed. Further, a ferroelectric film
18
of PZT or PLZT is formed on the lower electrode
17
, and an upper electrode
19
of Pt is formed on the ferroelectric film
18
.
The lower electrode
17
, the ferroelectric film
18
and the upper electrode
19
form together a ferroelectric capacitor C, wherein the ferroelectric capacitor is covered by a CVD-oxide film
21
including a side wall part thereof, and an interconnection pattern
20
makes an electrical contact with the upper electrode
19
via a contact hole formed in the CVD-oxide film
21
. Further, the entirety of the ferroelectric capacitor C is covered by an interlayer insulation film
22
.
The interlayer insulation film
22
includes a contact hole
22
A exposing the diffusion region
11
A, and a bit line pattern
23
of Al or an Al-alloy is formed on the interlayer insulation film
22
so as to make an electrical contact with the diffusion region
11
A at the contact hole
22
A.
FIG. 2
shows a unit cell of a PZT crystal used in the FeRAM
10
of
FIG.1
as the ferroelectric film
18
.
Referring to
FIG. 2
, the crystal of PZT has a perovskite structure, which is characterized by a phase transition in which a Ti or Zr atom occupying the site coordinated by O atoms undergoes a displacement in the direction of the c-axis. Thereby, the direction of the displacement depends on the direction of the external electric field applied to the PZT crystal, and thus, the PZT crystal exhibits a spontaneous polarization as represented in FIG.
3
. Thus, by applying a predetermined writing voltage across the lower electrode
17
and the upper electrode
19
, it is possible to reverse the polarization of the PZT crystal constituting the ferroelectric film
18
. In other words, it is possible to write desired binary information into the ferroelectric film
18
by applying such a predetermined writing voltage.
When reading out the binary information thus written into the FeRAM
10
of
FIG. 1
, the word line, and hence the gate electrode
13
of the memory cell transistor, is activated, and the voltage appearing at the bit line electrode
23
as a result of conduction of the channel region, is detected.
Referring to the hysteresis loop of
FIG. 3
, the height of the loop at the zero electric field strength is called the switching electric charge Q
SW
. The larger the value of the quantity Q
SW
, the better the reliability of information retention in the FeRAM
10
. Further, the electric field necessary for wiring information into the FeRAM
10
decreases with increasing values of Q
SW
. Thereby, the FeRAM
10
can be driven at a low voltage. Thus, in the FeRAM
10
of
FIG. 1
, it is desired to maximize the value of Q
SW
of the ferroelectric film
18
.
In order to obtain the spontaneous polarization represented in
FIG. 3
for the FeRAM
10
of
FIG. 1
, it is necessary to crystallize the ferroelectric film
18
in an oxidizing atmosphere at the temperature of at least 600° C. Thus, it has been practiced to form the lower electrode
17
by a refractive metal such as Pt, which shows a low reactivity against O
2
and maintains a low resist

Affiliated with

Also associated with

Rating

Ferroelectric capacitor having a PZT layer with an excess of Pb does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ferroelectric capacitor having a PZT layer with an excess of Pb, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric capacitor having a PZT layer with an excess of Pb will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3029578