Ferro-electric random access memory using paraelectric and...

Details Ferro-electric random access memory using paraelectric and... Ferro-electric random access memory using paraelectric and...

2005-02-08

2005-02-08

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S209000, C365S207000, C365S145000, C365S213000, C365S211000, C365S190000, C365S205000, C365S051000, C365S203000

Reexamination Certificate

active

06853600

ABSTRACT:
A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC1and a ferro-electric capacitor DCC2. One end of the paraelectric capacitor DCC1and one end of the ferro-electric capacitor DCC2are commonly connected to a node N1. A dummy plate electric potential DPL1is supplied to the other end of the paraelectric capacitor DCC1, and a dummy plate electric potential DPL2is supplied to the other end of the ferro-electric capacitor DCC2. When data of a memory cell MC is read at a bit line (selective bit line) BL1, a reference electric potential is supplied to a bit line (reference bit line) BL2from the dummy cell DC.

REFERENCES:
patent: 5768176 (1998-06-01), Katoh
patent: 5940316 (1999-08-01), Koike
patent: 6363002 (2002-03-01), Nishimura et al.
patent: 6594174 (2003-07-01), Choi et al.
patent: 9-134594 (1997-05-01), None
patent: 11-16377 (1999-01-01), None

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