Ferro-electric memory array architecture and method for forming

Details Ferro-electric memory array architecture and method for forming Ferro-electric memory array architecture and method for forming

1995-05-02

1997-04-08

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Ferroelectric

365 63, 365117, 365 65, 36523004, G11C 700

Patent

active

056194471

ABSTRACT:
A ferro-electric memory array (41) having a reduced size and increased performance is disclosed herein. The ferro-electric memory array (41) is arrayed in memory cell columns and memory cell rows. Each memory cell column shares a BIT or BITBAR line with an adjacent memory cell column. Two row enable lines are provided to each memory cell row. The row enable lines alternately couple to memory cells of a memory cell row to prevent a contention condition. Sharing BIT and BITBAR lines with adjacent memory cell columns reduces a width of the ferro-electric memory array (41) which reduces the resistance on each line CP for a memory cell row. The result is a memory array that is capable of operating at higher speeds. Also, using more than one row enable line in each row reduces the number of memory cells accessed in a read or write operation. This increases the endurance of the ferro-electric memory array (41) by a factor of two.

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Joseph T. Evans and Richard Womack, "An Experimental 512-bit Nonvolatile Memory with Ferroelectric Storage Cell", IEEE J. Solid-State Circuits,vol. 23, No. 5, pp. 1171-1175, Oct. 1988.

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