Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1992-11-18
1994-11-29
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257403, 257327, H01L 2978
Patent
active
053692950
ABSTRACT:
An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fermi FET is preferably implemented using a Fermi Tub having a predetermined depth, and with a conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source diffusions.
REFERENCES:
patent: Re32800 (1988-12-01), Han et al.
patent: 3653978 (1972-04-01), Robinson et al.
patent: 3789504 (1974-02-01), Jaddam
patent: 3872491 (1975-03-01), Hanson et al.
patent: 4042945 (1977-08-01), Lin et al.
patent: 4108686 (1978-08-01), Jacobus, Jr.
patent: 4274105 (1981-06-01), Crowder et al.
patent: 4697198 (1987-09-01), Komori et al.
patent: 4701775 (1987-10-01), Cosentino et al.
patent: 4737471 (1988-04-01), Shirato et al.
patent: 4819043 (1989-04-01), Yazawa et al.
patent: 4831422 (1989-05-01), Ohno
patent: 4841346 (1989-06-01), Noguchi
patent: 4899202 (1990-02-01), Blake et al.
patent: 4907048 (1990-03-01), Huang
patent: 4928156 (1990-05-01), Alvis et al.
patent: 4984043 (1991-01-01), Vinal
patent: 4990974 (1991-02-01), Vinal
patent: 4994872 (1991-02-01), Nishizawa et al.
patent: 5151759 (1992-09-01), Vinal
patent: 5194923 (1993-03-01), Vinal
Depleted Implant MOSFET, IBM Technical Disclosure Bulletin, vol. 32, No. 10B, Mar., 1990, pp. 235-249.
High Performance Subhalf-Micrometer P-Channel Transistors for CMOS VLSI, A. E. Schmitz et al.; IEDM 84, pp. 423-426, 1984.
Characteristics of P-Channel MOS Field Effect Transistors with Ion-Implanted Channels, Hswe, M. et al., Solid-State Electronics, vol. 15, pp. 1237-1243, 1972.
The Junction MOS (JMOS) Transistor-A High Speed Transistor for VLSI, Sun, E. et al., IEEE, pp. 791-794, 1980.
Optimization of Sub-Micron P-Channel FET Structure, Chiang, S. et al., IEEE, pp. 534-535, 1983.
Gate Material Work Function Considerations for 0.5 Micron CMOS, Hillenius, S. J. et al., IEEE, pp. 147-150, 1985.
A Normally-Off Type Buried Channel MOSFET for VLSI Circuits, Nishiuchi, K. et al., IEDM Technical Digest, 1979, pp. 26-29.
Ultra-High Speed CMOS Circuits in Thin SIMOX Films, A. Kamgar et al., IEDM vol. 89, pp. 829-832, 1989.
Fabrication of CMOS on Ultrathin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing, G. Shahidi, IEDM vol. 90, pp. 587-590, 1990.
Submicron MOSFET Structure for Minimizing Channel Hot-Electron Injection, Takeda E., et al., 1981 Symposium on VLSI Technology, Hawaii (Sep. 1981), Dig. Tech. Papers pp. 22-23.
A New Half-Micrometer P-Channel MOSFET with Efficient Punchthrough Stops, Odanaka S., et al., IEEE Transactions on Electron Devices, vol. ED-33, No. 3, Mar., 1986, pp. 317-321.
Bowers Courtney A.
Jackson Jerome
Thunderbird Technologies, Inc.
LandOfFree
Fermi threshold field effect transistor with reduced gate and di does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fermi threshold field effect transistor with reduced gate and di, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fermi threshold field effect transistor with reduced gate and di will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-75624