FeRAM with a single access/multiple-comparison operation

Details FeRAM with a single access/multiple-comparison operation FeRAM with a single access/multiple-comparison operation

2002-04-02

2004-03-09

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090, C365S210130, C365S189070

Reexamination Certificate

active

06704218

ABSTRACT:

BACKGROUND
A conventional FeRAM has memory cells containing ferroelectric capacitors. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates. To store data in a memory cell, a write operation applies write voltages to the plates of the ferroelectric capacitor to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed, which in turn maintains charge on the conductive plates.
A conventional read operation for a FeRAM cell connects one plate of a ferroelectric capacitor to a bit line and raises the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large current and voltage increase on the bit line. A sense amplifier can sense the stored value from the resulting bit line current or voltage.
FIG. 1A
illustrates a portion of a conventional FeRAM
100
that includes memory cells
110
arranged in rows and columns to form a memory array. Only one column and two rows of memory cells
110
are shown in
FIG. 1A
for simplicity of illustration, but a typical FeRAM array may include hundreds or thousands of columns of memory cells with a similar number of rows. Each memory cell
110
of FeRAM
100
includes a ferroelectric capacitor
112
and a select transistor
114
. Each select transistor
114
has a gate connected to a word line
116
corresponding to the row containing the memory cell and a source/drain connected to a bit line
120
corresponding to the column containing the memory cell.
A conventional read operation accessing a selected memory cell
110
in FeRAM
100
biases a plate of the selected memory cell to a plate voltage Vp (e.g., 3 V), and activates a selected word line
116
to turn on a select transistor
114
thereby electrically connecting the selected ferroelectric capacitor to bit line
120
. The difference between the plate voltage and the initial bit line voltage forces the persistent polarization in the selected ferroelectric capacitor into a first state. Bit line
120
acquires a voltage that depends on the initial polarization state of the selected memory cell
110
. In particular, if the selected memory cell was in a second state having a persistent polarization in a direction opposite to the persistent polarization of the first state, forcing the memory cell from the second state into the first state causes a relatively large current to bit line
120
and a corresponding rise in the bit line voltage. If the selected memory cell was already in the first state, a relatively small current flows to bit line
120
.
A sense amplifier
130
connected to the bit line
120
compares the bit line voltage to a reference voltage Vref. A reference voltage generator (not shown) can generate reference voltage Vref at a level that is above the bit line voltage read out when the selected memory cell
110
has the first polarization state and below the bit line voltage read out when the selected memory cell
110
has the second polarization state. In sense amplifier
130
, cross-coupled transistors drive bit line
120
to a logic level (high or low) depending on whether the bit line voltage was greater or less than reference voltage Vref. A bit thus read has a value indicated by the voltage on the bit line after operation of the sense amplifier.
FIG. 1B
illustrates an alternative memory
100
′ in which each memory cell
110
′ includes two ferroelectric capacitors
112
and
112
′ connected through respective select transistors
114
and
114
′ to respective bit lines
120
and
120
′. A write operation forces ferroelectric capacitor
112
′ to a polarization state that is complimentary to the polarization state of ferroelectric capacitor
112
. A read operation applies plate voltage Vp to both ferroelectric capacitors
112
and
112
′ and activates a selected word line
116
to turn on select transistors
114
and
114
′ and electrically connect selected ferroelectric capacitors
112
and
112
′ to bit lines
120
and
120
′, respectively. The read operation thus forces both ferroelectric capacitors
112
and
112
′ to the first polarization state. The bit line
120
or
120
′ connected to the ferroelectric capacitor
112
or
112
′ initially in the second polarization state rises to a higher voltage. Sense amplifier
130
drives the bit lines
120
and
120
′ connected to the memory cell initial in the second polarization state to complementary voltage, where the voltage on bit line
120
indicates the data bit read from the memory cell.
A read operation for FeRAM cell
110
or
110
′ of
FIG. 1A
or
1
B generally requires a write-back operation to restore a persistent polarization of a ferroelectric capacitor to the second state if the read operation forced the ferroelectric capacitor from the second state to the first state. In FeRAMs like
100
and
100
′, sense amplifier
130
drives the bit lines
120
and
120
′ to voltage suitable for the write-back operations. However, the driven voltage can interfere with uses of FeRAM that may require comparing a read-out bit line voltage to multiple different reference voltages. For example, an on-chip bit failure prediction, detection, and correction method might need to compare the read-out voltage from a memory cell to a series of reference voltages to determine whether the polarization state of the memory cell provides a bit line voltage large enough for an accurate read operation.
Using conventional read operations for comparisons to multiple reference voltages requires repeating the steps of reading a voltage out of a selected memory cell
110
to a bit line and sense amplifier, applying the first or next reference voltage to the sense amplifier, and comparing the read-out voltage to the applied reference voltage. Repetition of these operations is generally too slow for on-chip bit failure correction techniques. Additionally, write-back operations and time dependent failure mechanisms in ferroelectric materials make the charge delivered to a bit line or the voltage read out from a FeRAM cell vary from access to access, particularly because the polarization state of the FeRAM cell is refreshed between comparisons. The comparisons to different reference voltages thus may be inconsistent.
In view of the limitations to current read processes for FeRAM, improved processes and circuits for performing multiple comparisons are desired.
SUMMARY
In accordance with an aspect of the invention, a read out voltage from a ferroelectric capacitor is compared to multiple reference voltages using a sense amplifier that does not disturb the read out voltage on a bit line. Accordingly, a fast series of comparisons can be performed to characterize the performance of an FeRAM cell, to anticipate or detect a bit error, or to read a multi-bit or multi-level value from a single ferroelectric capacitor.
The multiple-comparison operation includes reading out a voltage to a bit line that is otherwise floating and is coupled to a gate of a transistor in a sense amplifier. The read out voltage can be maintained while a series of reference voltages are applied to the sense amplifier for a series of sensing or comparison operations. When the series of operations is complete, a write-back operation restores the polarization state in the selected FeRAM cell.
One specific embodiment of the invention is a device including a bit line connected to FeRAM cells, a reference voltage generator capable of generating a series of voltage levels, and a sense amplifier c

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