Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-26
2004-06-08
Pert, Evan (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S003000, C365S145000
Reexamination Certificate
active
06747302
ABSTRACT:
TECHNICAL FIELD
A ferroelectric random access memory (FeRAM), more particularly, a method for forming a FeRAM having a (Bi
x
La
y
)Ti
3
O
12
(BLT) ferroelectric layer is disclosed.
DESCRIPTION OF THE RELATED ART
A ferroelectric random access memory (FeRAM) is a nonvolatile semiconductor memory device with high integration of a dynamic random access memory (DRAM), a high speed information process of a static random access memory (SRAM) and an information storing function of a flash memory. As compared with a conventional flash memory and an electrically erasable programmable read only memory (EEPROM), a FeRAM has a relatively low operation voltage and its operation speed is 1000 times as fast as a flash memory or an EEPROM.
When voltage is applied to a DRAM capacitor, which includes a dielectric layer, such as a SiO
2
layer or a SiON layer, and then the voltage supply is terminated, the charges in the DRAM capacitor are discharged so that data stored in the DRAM are lost.
The ferroelectric material has two stabilized remnant polarization states.
Being different from the DRAM capacitor, the ferroelectric capacitor in the FeRAM maintains previously stored data by the remnant polarization of a ferroelectric material even if power supply is terminated.
The FeRAM device is similar to the DRAM device in that a transistor and a capacitor are connected to a word line and a plate line, respectively. However, the FeRAM device is different from the DRAM device in that a capacitor has a ferroelectric thin layer and the plate line is not connected to ground voltage or fixed voltage, e.g., ½ Vcc, and each cell is connected to a separate plate line so that power can be applied to the separate plate line on a cell-by-cell basis.
FIG. 1A
is a circuit diagram illustrating a memory cell structure of a conventional FeRAM device including one transistor and one ferroelectric capacitor.
The transistor (Tr) includes a gate electrode connected to a word line (WL), a source and a drain, which are respectively connected to a bit line (BL) and a capacitor (C). The capacitor (C) includes a bottom electrode connected to a plate line (PL), a top electrode connected to the transistor (Tr) and a ferroelectric layer formed between the bottom electrode and the top electrode. The top electrode of the capacitor (C) functions as a charge storage electrode.
FIG. 1B
is a cross-sectional view showing a FeRAM according to the prior art. A semiconductor substrate
10
including a field oxide layer
11
and a transistor having a gate insulating layer
12
, a gate electrode
13
and source/drain
14
, is provided. A first interlayer insulating layer
15
is formed on the semiconductor substrate
10
and an adhesive layer
16
in formed on the first interlayer insulating layer
15
. A capacitor including a bottom electrode
17
, a ferroelectric layer
18
and a top electrode
19
formed on the adhesive layer
16
are formed. A second interlayer insulating layer
20
is formed on the resulting structure. A first contact hole exposing the top electrode
19
of the capacitor and a second contact hole exposing the source/drain
14
formed on the semiconductor substrate
10
are formed. A metal diffusion barrier layer
21
with a stacked structure of Ti layer and TiN layer is layered and an interconnection line
22
connecting the top electrode of the capacitor with the source/drain of the transistor is formed.
FIG. 2
is a graph showing a hysteresis loop of a ferroelectric capacitor. In
FIG. 2
, positive voltage is defined when a potential of a bit line is higher than that of a plate line and remnant polarizations at points, “a” and “c”, are defined to data “1” and “0”, respectively.
If a transistor is turned on and positive voltage is applied to a plate line, then negative voltage applied to the ferroelectric capacitor and a charge variation is passing through point “d” in the hysteresis loop. After that, in case of turning the applied voltage to “0 V”, polarization is going to the point “a” and the data “1” is stored. Meanwhile, when the data “0” is inputted, a positive voltage is applied to a ferroelectric capacitor and a charge variation is passing through point “b”, and turning the applied voltage to “0 V”, then a polarization value is going to point “c” and data “0” is stored.
When the voltage is applied to the ferroelectric capacitor, data writing is carried out by detecting a voltage variation on the bit line. That is, if positive voltage is applied to the capacitor, in case the data is “0”, the charge variation of &Dgr;Q
1
is detected. That is, the charge variation on the bit line is determined by information stored on the capacitor.
The charge variation due to the remnant polarization of the ferroelectric capacitor changes a voltage level on the bit line. Typically, parasite capacitance “Cb” is existed on the bit line itself. When the transistor is turned on and a memory to be read out is selected, charges as much as of &Dgr;Q
1
or &Dgr;Q
0
are outputted. Bit line voltages “V1” and “V2” are acquired by dividing the &Dgr;Q
1
and the &Dgr;Q
0
with the sum of bit line capacitance (Cb) and ferroelectric capacitor (C) capacitance “Cs” and is given by:
V
1
=&Dgr;Q
1
/(
Cb+Cs
)
V
2
=&Dgr;Q
0
/(
Cb+Cs
)
Therefore, the potential on the bit line is varied according to the difference between the data “1” and “0”. When the transistor is turned on by applying voltage to the word line, potential on the bit line is changed to the “V1” or the “V0”. In order to determine whether potential on the bit line is in a voltage level of “V1” or “V0”, a reference voltage (Vref), which is set to a specific voltage level between the voltage levels “V1” and “V0”, is used.
Pb(Zr, Ti)O
3
(hereinafter, referred to as a PZT) or SrBi
2
(Ta
2
, Nb)O
9
(hereinafter, referred to as an SBTN) and SrBi
2
Ta
2
O
9
(hereinafter, referred to as a SBT) of Bi-layered series thin layer are mainly used as a dielectric material of the FeRAM. The material property of a bottom layer disposed under a ferroelectric layer is important in crystallizing the ferroelectric layer. That is, in the ferroelectric capacitor, the characteristic of the ferroelectric layer is largely affected by the electrode, so the electrode must have a low resistance, a small lattice mismatch between the ferroelectric material and the electrode, a high heat-resistance, a low reactivity, a high diffusion barrier characteristic and a good adhesion between the electrode and a ferroelectric material.
As mentioned in the above, the PZT of Pb-series or the SBT and SBTN having the Bi-layered structure are developed as dielectric materials of the capacitor in the nonvolatile memory device. However, the Pb-series ferroelectric layers are difficult to apply because fatigue, retention and imprint properties, related to the lifetime of device, are inferior. Even if the SBT series has good confidence and properties, compared with the other ferroelectric materials, it is also difficult to apply, since layers, previously formed for a capacitor, are oxidized during the thermal treatment performed over 800° C. to crystallize ferroelectric layers.
Especially, in case using the plug structure for connecting the bottom electrode of the capacitor with the source/drain of the transistor, the plug is oxidized during thermal treatment process for nucleation and grain growth. The prior art, as described in
FIG. 1B
, the top electrode
19
of the capacitor is connected to the source/drain
14
of the transistor to prevent the oxidation of the plug, however, the prior art has the demerit of device size increasing.
SUMMARY OF THE DISCLOSURE
A ferroelectric memory device having a (Bi
x
La
y
)Ti
3
O
12
(hereinafter, referred as a BLT) layer which improves the electric characteristic of the device and that can be crystallized at relative low temperature is disclosed.
A method for manufacturing ferroelectric memory device is also disclosed which comprises: a) forming a first conductive layer for a bottom electrode on a semiconductor substrate; b) forming a (Bi
x
La
y
)Ti
3
O
1
Kim Nam-Kyeong
Kweon Soon-Yong
Yang Woo-Seok
Yeom Seung-Jin
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Pert Evan
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