Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-09-10
2003-04-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000, C365S149000
Reexamination Certificate
active
06549448
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a ferroelectric random access memory (FeRAM) and, more particularly, to a FeRAM having adjacent memory cells sharing cell plate and a driving method for the same.
DESCRIPTION OF THE PRIOR ART
A ferroelectric random access memory (FeRAM) is a nonvolatile semiconductor memory device with a highly integrated dynamic random access memory (DRAM), the speedy information processing of a static random access memory (SRAM), and the information storing function of a flash memory. As compared with a conventional flash memory and an electrically erasable programmable read only memory (EEPROM), the FeRAM has a relatively low operational voltage and an operating speed that is about 1000 times faster.
When voltage is applied to a DRAM capacitor, which includes a dielectric layer such as a SiO
2
layer or a SiON layer, and then the voltage supply is terminated, the charges in the DRAM capacitor are discharged so that data stored in the DRAM are lost.
The ferroelectric material has two stabilized remnant polarization states at room temperature. Unlike the DRAM capacitor, the ferroelectric capacitor in the FeRAM maintains previously stored data by the remnant polarization of a ferroelectric material even if the power supply is terminated.
FIG. 1
is a graph showing a hysteresis loop of a ferroelectric capacitor. In
FIG. 1
, positive voltage is defined when the potential of a plate line is higher than that of a bit line and the remnant polarizations at points “a” and “c”, are defined to data “1” and “0”, respectively.
If the transistor is turned on and a negative voltage is applied to the plate line “PL”, then a negative voltage is also applied to the ferroelectric capacitor and a charge variation passes through point “d” in the hysteresis loop. After that, in case of turning the applied voltage to “0 V”, a polarization value goes to point “a” and the data “1” is stored. Meanwhile, when the data “0” is inputted, a positive voltage is applied to the ferroelectric capacitor and the charge variation passes through point “b” and, turning the applied voltage to “0 V”, then a polarization value goes to point “c” and the data “0” is stored.
When the voltage is applied to the ferroelectric capacitor, data are written by detecting the voltage variation on the bit line. That is, if positive voltage is applied to the capacitor, in case the data is “0”, the charge variation of &Dgr;Q
0
is detected. That is, the charge variation on the bit line is determined by information stored on the capacitor. The charge variation due to the remnant polarization of the ferroelectric capacitor changes a voltage level on the bit line. Typically, parasite capacitance “C
BL
” exists on the bit line itself. When the transistor is turned on and a memory to be read out is selected, charges of as much as &Dgr;Q
1
or &Dgr;Q
0
are outputted. Bit line voltages “V
BL1
” and “V
BL0
” are acquired by dividing the &Dgr;Q
1
and the &Dgr;Q
0
with the sum of bit line capacitance “C
BL
” and ferroelectric capacitor capacitance “Cs” and is given by:
V
BL1
=&Dgr;Q
BL1
/(
C
BL
+Cs
)
V
BL0
=&Dgr;Q
BL0
/(
C
BL
+Cs
)
Therefore, the potential on the bit line is varied according to the difference between the data “1” and “0”. When the transistor is turned on by applying voltage to the word line, potential on the bit line is changed to the “V
BL1
” or the “V
BL0
”. In order to determine whether the potential on the bit line is in a voltage level of “V
BL1
” or “V
BL0
”, a reference voltage “V
ref
”, which is set to a specific voltage level between the voltage levels “V
BL1
” and “V
BL0
”, is used.
SrBi
2
Ta
2
O
9
(hereinafter, referred to as an SBT) or Pb(Zr, Ti)O
3
(hereinafter, referred to as a PZT) is mainly used as a dielectric material for the FeRAM. The material property of the bottom layer disposed under a ferroelectric layer is important to crystallize the ferroelectric layer. That is, in the ferroelectric capacitor, the characteristic of the ferroelectric layer is largely affected by the electrode, so it is necessary to have sufficiently low resistance, a small lattice mismatch between the ferroelectric material and the electrode, a high heat-resistance, a low reactivity, a high diffusion barrier characteristic and a good adhesion between the electrode and the ferroelectric material.
FIG. 2A
is a circuit diagram of a conventional FeRAM having adjacent memory cells of which plate lines are separated. Each transistor Tr
1
, Tr
2
, in adjacent memory cells CELL
0
, CELL
1
, includes a gate electrode respectively connected to a word line WL
0
, WL
1
, a source commonly connected to a bit line BL
0
and a drain respectively connected to an electrode of a capacitor C
1
, C
2
. Each capacitor C
1
, C
2
includes a first electrode connected to cell plate line CP
0
, CP
1
, a second electrode connected to the transistor Tr
1
, Tr
2
and a ferroelectric layer formed between the first electrode and the second electrode. The second electrode of the capacitors C
1
, C
2
, respectively connected to the transistors Tr
1
, Tr
2
, functions as a charge storage electrode.
FIG. 2B
is a layout of the FeRAM shown in FIG.
2
A.
The driving method of a FeRAM differs from a DRAM. In the case of the DRAM, a word line is selected to operate a memory cell when the voltage of a plate line connected to the memory cell is already fixed to a half of the operating potential Vcc. The voltage of a bit line in the DRAM becomes higher or lower than Vcc/2 according to stored data “1” and “0”. But, in the case of the FeRAM, the voltage of the cell plate line is varied from “0 V” to the operating potential “Vcc” after a word line is selected.
Also, a sense amplifier of the DRAM compares the voltage of the bit line with the voltage of the bit bar line, of which voltage is fixed to the “Vcc/2”, and amplifies the voltage difference between the bit line and bit bar line to detect the stored data, whether the stored data is “1” or “0”. But, the voltage of the bit line in the FeRAM is increased regardless of whether the stored data “1” or “0”. However, the amount of voltage increase depends on the stored data “1” or “0”, such that the voltage increase amount is relatively high when the stored data is “1”. Therefore, a reference voltage generator, generating a voltage value between the data “1” and “0”, is needed to provide a reference voltage.
The time for driving a cell plate line increases in proportion to the capacitance of the cell plate line. Therefore, a line shaped cell plate is formed to reduce the capacitance and to increase speed. Also, a method is provided to select and to drive a cell plate line whenever a memory cell is selected.
FIG. 3
is a cross-sectional view of the FeRAM shown in FIG.
2
A and the layout shown in FIG.
2
B.
A semiconductor substrate
10
including an isolation layer
11
and a transistor having a gate insulating layer (not shown), word lines WL
0
, WL
1
and source/drain
12
, is provided. A first interlayer insulating layer
13
is formed over the semiconductor substrate
10
, and a capacitor, including a bottom electrode
14
, a ferroelectric layer
15
and a top electrode
16
, is formed. The bottom electrode
14
is connected to cell plate line CP
0
, CP
1
and the top electrode
16
is connected to a storage node. A second interlayer insulating layer
17
is formed on the resulting structure. A first contact hole exposing the top electrode
16
and a second contact hole exposing the source/drain
12
are formed. A metal diffusion barrier layer
18
, an interconnection line
19
A connecting the top electrode of the capacitor with one of the source/drain
12
and a bit line plug
19
B connecting to the other source/drain, are formed. Thereafter, a third interlayer insulating layer
20
and a bit line BL
0
, connected to the bit line plug
19
B, are formed.
Generally the DRAM has a structure referred to as COB, that is, the capacitor of the DRAM is formed over the bit line. By contrast, the FeRAM has a structure referred to as CUB, that is, the capacitor of
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
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