FeRAM capacitor stack etch

Details FeRAM capacitor stack etch FeRAM capacitor stack etch

2006-04-18

2006-04-18

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

07029925

ABSTRACT:
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

REFERENCES:
patent: 5658820 (1997-08-01), Chung
patent: 6211035 (2001-04-01), Moise et al.
patent: 6261967 (2001-07-01), Athavale et al.
patent: 6284654 (2001-09-01), Roeder et al.
patent: 6316797 (2001-11-01), Van Buskirk et al.
patent: 6320213 (2001-11-01), Kirlin et al.
patent: 6326218 (2001-12-01), Yunogami et al.
patent: 6436838 (2002-08-01), Ying et al.
patent: 6458516 (2002-10-01), Ye et al.
patent: 6656748 (2003-12-01), Hall et al.
patent: 2001/0034106 (2001-10-01), Moise et al.
patent: 2002/0006674 (2002-01-01), Ma et al.
patent: 0 889 506 (1999-01-01), None
“FeRAM Tutorial”, Ali Sheikholeslami and P. Glenn Gulak, A Survey of Circuit Innovations in Ferroelectric Random-Access Memories, Proceedings of the IEEE, vol. 88, No. 3, May, 2000, 3 pgs. reprinted from the Internet at: http://www.eecg.toronto.ed/-ali/ferro.tutorial.html.
“A Survey of Circuit Innovations in Ferroelectric Random-Access Memories”, Ali Sheikholeslami and P. Glenn Gulak, Proceedings of the IEEE, vol. 88, No. 5, May, 2000, pp. 667-689.
“Effects of BCl3Addition on Ar/Cl2Gas in Inductively Coupled Plasmas for Lead Zirconate Titanate Etching”, Tae-Hyun An, Joon-Yong Park, Geun-Young Yeom, Eui-Goo Chang and Chang-ll Kim, Journal of Vacuum Science and Technology: Part A, American Institute of Physics, vol. 18, No. 4, Jul., 2000, pp. 1373-1376.
Reactive Ion Etching of Pt/PZT/Pt Ferroelectric Thin Film Capacitors in High Density DECR Plasma, H. Mace, H. Achard and L. Peccoud, Microelectronic Engineering, Elsevier Publishers BV, Amsterdam NL, vol. 29, No. 1, Dec. 1, 1995, pp. 45-48.
“Device Processing and Integration of Ferroelectric Thin Films for Memory Applications”, H. Achard, H. Made and L. Peccoud, Microelectronic Engineering, Elsevier Publishers BV, Amsterdam, NL., vol. 29, No. 1, Dec. 1, 1995, pp. 19-28.
“Plasma Etch Processing of Advanced Ferroelectric Devices”, Alferd Cofer, Paritosh Rajora, Steve Deornellas and Doug Keil, Integrated Ferroelectrics, 1997, vol. 16, 9pgs.
European Search Report, Application No. 03100194.4, Texas Instruments Corp. Ref. TI-33650EP, 3 pgs.
European Search Report, Application No. 03100194.4, Texas Instruments Corp. Ref. TI-33650EP, 3 pgs.

Affiliated with

Also associated with

Rating

FeRAM capacitor stack etch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FeRAM capacitor stack etch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FeRAM capacitor stack etch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3525259