Fencepost descriptor caching mechanism and method therefor

Details Fencepost descriptor caching mechanism and method therefor Fencepost descriptor caching mechanism and method therefor

2005-09-06

2005-09-06

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S024000, C709S213000, C711S129000, C711S147000

Reexamination Certificate

active

06941391

ABSTRACT:
A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.

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