Feedforward limited switch dynamic logic circuit

Details Feedforward limited switch dynamic logic circuit Feedforward limited switch dynamic logic circuit

2005-07-19

2005-07-19

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S121000, C327S208000

Reexamination Certificate

active

06919739

ABSTRACT:
The N channel field effect transistor (NFET) of the inverting output stage of a LSDL gate is split into a large NFET and a small NFET. The large NFET is coupled to a feedforward pulse so that it is turned ON only when the inverting output is a logic one. When the inverting output is a logic one, another inverting stage turns ON if the dynamic node evaluates to a logic zero. The dynamic node is inverted and coupled to the large NFET on the inverting output stage thus quickly pulling the inverting output to a logic zero. The small NFET is turned ON as a keeper device through the normal logic path. If the inverting data output is a logic zero the feedforward pulse is not generated. By making the largest NFET a pulsed device the other FETs are reduced in size resulting in leakage and switching power savings.

REFERENCES:
patent: 6498514 (2002-12-01), Alvandpour
patent: 6686775 (2004-02-01), Campbell
patent: 6690204 (2004-02-01), Belluomini et al.
patent: 6690205 (2004-02-01), Alvandpour
patent: 6717442 (2004-04-01), Campbell
patent: 6833735 (2004-12-01), Kumar et al.

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