Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2000-01-21
2002-10-15
Lee, Michael G. (Department: 2876)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S093000, C326S095000, C326S098000
Reexamination Certificate
active
06466057
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to digital logic circuits, for example but not limited to, integrated circuits (ICs), and more particularly, to a new family of pseudo-NMOS static logic gates that use feedback from a shared node that produces the output in order to enhance the response speed of and applicability of such gates.
BACKGROUND OF THE INVENTION
Static logic gates based upon CMOS (complementary metal oxide semiconductor) technology are generally slow because an input must drive both NMOS (n-channel MOS) arid PMOS (p-channel MOS) field effect transistors (FETs). In any transition, either a pullup PMOS transistor network or a pulldown NMOS transistor network is activated, which means that the input capacitance of the inactive network loads the input. Moreover, PMOS transistors have poor mobility and must be wider than NMOS transistors to achieve comparable rising and falling delays, further increasing input capacitance. Pseudo-NMOS static logic gates and dynamic logic gates, which require a precharge, offer improved speed by removing the PMOS transistor load from the input.
Pseudo-NMOS gates resemble CMOS gates, but replace the slow PMOS pullup transistor(s) with a grounded PMOS transistor(s) that acts as a pullup resistor. The effective pullup resistance should be large enough that the NMOS transistor(s) can pull the output to near ground, yet low enough to pull the output to high voltage quickly. Margin must be provided for manufacturing variations in the relative PMOS and NMOS mobilities. In addition, a pseudo-NMOS gate is smaller than a CMOS gate, making it even more desirable than a CMOS gate in some implementations.
Although meritorious to an extent, pseudo-NMOS static logic gates have disadvantages and limited applicability. Typically, they are used by logic circuit designers only selectively for high fan-in logic functions. The reason is that the output of a pseudo-NMOS static logic gate must be capable of, after performing a logic evaluation upon its inputs, exhibiting high voltage (for a logic high) or transitioning from high voltage to low voltage (for a logic low). In order to accomplish this functionality while observing the aforementioned resistance limitations, the pullup network typically requires a PMOS transistor(s) having a large width in order to pull up quickly, but this large PMOS transistor(s) then impedes the pull down speed, which is driven by the NMOS transistor(s). The result is a difficult and efficient compromise, because as is well known in the art, in order to achieve a PMOS transistor with the same drive strength as an NMOS transistor, the PMOS transistor must be at least twice the width of the corresponding NMOS transistor. Consequently, a static logic gate should have a fan-in of ten or more NMOS transistors before a pseudo-NMOS gate is better in terms of speed than a static CMOS transistor implementation.
SUMMARY OF THE INVENTION
The present invention provides a new family of pseudo-NMOS static logic gates that use feedback from a shared node to enhance the response of and applicability of such static logic gates. In fact, because of the enhanced performance of the feedback-induced pseudo-NMOS static (FIPNS) logic gates in accordance with the present invention, the FIPNS logic gates are more desirable than CMOS transistor implementations when the fan-in of NMOS transistors is much lower that prescribed by conventional wisdom.
In architecture, broadly stated, the FIPNS logic gate comprises at least (a) a pulldown network having one or more pulldown NMOS transistors for receiving one or more inputs, (b) a primary pullup network having one or more primary pullup PMOS transistors connected to the NMOS transistor network at a shared node, which produces a gate output, and (c) a secondary pullup network having one or more secondary pullup PMOS transistors connected to said NMOS transistor network by way of a suitable actuation mechanism, which causes actuation of the secondary pullup PMOS transistor(s) based upon feedback from the shared node to thereby increase pullup drive strength relative to pulldown drive strength. In the preferred embodiment (a nonlimiting example), the actuation mechanism is merely a delay mechanism comprising one or more cascaded logic gates. The FIPNS logic gate can be configured and used to perform any type of logic function upon one or more inputs. the present invention can also be conceptualized as providing one or more new methods. As an example of one such method, the present invention can be viewed as providing a method for enhancing the applicability and speed of a pseudo-NMOS logic gates, comprising at least the steps of: (a) providing a static logic gate comprising a pulldown network having at least one or more pulldown NMOS transistors for receiving one or more inputs and a pullup network having at least one or more pullup PMOS transistors connected to the NMOS transistor network at a shared node for producing an output; and (b) dynamically increasing pullup drive strength relative to the pulldown drive strength based upon feedback from the shared node.
Other features, advantages, systems, and methods that are provided by the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features, advantages, systems, and methods be included herein within the scope of the present invention.
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Lee Michael G.
Paik Steven S.
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