Feedback cycle detection across non-scan memory elements

Details Feedback cycle detection across non-scan memory elements Feedback cycle detection across non-scan memory elements

2006-01-10

2006-01-10

Dildine, R. Stephen (Department: 2133)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C702S059000, C703S015000, C703S022000, C716S030000

Reexamination Certificate

active

06986114

ABSTRACT:
All feedback cycles in a circuit network which cross only non-scannable memory elements are detected in linear run time. The method models a circuit network as a directed graph, then attributes network elements so that a single feedback cycle may be found in constant time. In the breadth first version, feedback is detected by traversing at most a constant distance back to the last scannable memory element. In the depth first version, graph nodes are not FINISHED until all predecessors are FINISHED. Feedback is found immediately if a node runs into another node that is NOT—FINISHED. This feedback is illegal if both nodes are in a zone defined by the same scannable memory element. The resulting identification and removal of feedback loops crossing only non-scannable memory elements significantly reduces the subsequent complexity of test pattern generation. This ensures a faster, more reliable, and more accurate test process after circuit fabrication.

REFERENCES:
patent: 6910193 (2005-06-01), McBride
patent: 2003/0179707 (2003-09-01), Bare
patent: 2001358581 (2001-12-01), None
Concurrent Detection of Feedback Loops in Directed Graphs; IBM Technical Disclosure Bulletin, Apr. 1991; vol. 33, No. 1, pp. 338-340.

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