Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-08-20
2001-09-18
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S017000, C438S784000
Reexamination Certificate
active
06291253
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to the field of semiconductor processing, and, more particularly, to planarization operations in semiconductor processing operations.
2. Description of the Related Art
Chemical mechanical polishing (“CMP”) is widely used in semiconductor processing operations to planarize various process layers, e.g., silicon dioxide, formed above a wafer comprised of a semiconducting material, such as silicon. Chemical mechanical polishing operations typically employ an abrasive slurry distributed in an alkaline or acidic solution to planarize the surface of a process layer through a combination of mechanical and chemical actions.
FIG. 1
is a schematic drawing of one illustrative embodiment of a chemical mechanical polishing tool used in semiconductor processing operations. As depicted therein, the illustrative polishing tool
10
is comprised of a rotatable table
12
on which an illustrative polishing pad
14
is mounted, and a multi-head carrier
16
positioned above the pad
14
. The multi-head carrier
16
includes a plurality of rotatable polishing arms
18
, each of which includes a carrier head
20
. Typically, wafers (not shown) are secured to the carrier heads
20
by the use of vacuum pressure. This is sometimes referred to as the carrier backforce pressure. In use, the table
12
is rotated and an abrasive slurry is dispensed onto the polishing pad
14
. Once the slurry has been applied to the polishing pad
14
, a downforce is applied to each rotating polishing arm
18
to press its respective wafer against the polishing pad
14
. As the wafer is pressed against the polishing pad
14
, the surface of the process layer on the wafer is mechanically and chemically polished. Although the tool depicted in
FIG. 1
is a multi-head polishing tool
10
, similar single-head type machines exist in the industry, and the present invention is not limited to any particular embodiment, form or structure of a tool that may be used to perform chemical mechanical polishing operations.
The continual drive to reduce feature sizes, e.g., channel length, on semiconductor devices has increased the importance of chemical mechanical polishing or planarization in the semiconductor fabrication process. For example, as feature sizes tend to decrease, the depth of field of photolithography equipment tends to shrink, thereby necessitating a very flat or planar surface so that very small dimensions may be accurately patterned on a wafer. Additionally, there has been, and continues to be, a constant drive to increase the productivity of fabrication techniques employed in making modern semiconductor devices. In short, there is a constant drive within the industry to make the same high-quality semiconductor products, but to do it faster, better, and in a less expensive manner.
One problem encountered in modem processing operations is that process films yet to be planarized are sometimes made excessively thick to compensate for variations in the planarization operation performed by a planarization tool, e.g., a CMP tool. For example, a process layer may be made relatively thicker to allow the planarization tool sufficient time to produce a planar surface before reaching the desired final thickness of the process layer after planarization. The formation of the additional thickness of the process layer prior to planarization results in an increase in time and materials to initially form the layer, and an increase in the planarization time and amount of consumable materials used in the planarization process.
The present invention is directed to a method of solving, or at least reducing, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to semiconductor processing operations, particularly in the area of manufacturing process layers comprised of a variety of materials, and planarizing a surface of such a process layer. More particularly, in one illustrative embodiment, the present invention is directed to determining a planarization efficiency of a planarization operation, and manufacturing a process layer to a thickness based upon the determined planarization efficiency of the planarization operation.
REFERENCES:
patent: 6057068 (2000-05-01), Reader et al.
Evans Allen L.
Lansford Jeremy
Advanced Micro Devices , Inc.
Lebentritt Michael
Williams Morgan & Amerson P.C.
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