FEC frame structuring method and FEC multiplexer

Details FEC frame structuring method and FEC multiplexer FEC frame structuring method and FEC multiplexer

2005-03-15

2005-03-15

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S776000

Reexamination Certificate

active

06868514

ABSTRACT:
In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit32, a first error correction code is generated by an RS (239, 223) coding circuit33, the order is returned to the original order by a first deinterleaving circuit34, and a second error correction code is generated by an RS (255, 239) coding means5. The second error correction code is decoded by an RS (255, 239) decoding circuit11to correct errors in the information, the order of information is changed by a second interleaving circuit35, the first error correction code is decoded by an RS (239, 223) decoding circuit36to correct residual errors in the information, and the order is returned to the original order by a second deinterleaving circuit37.

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Sab et al., ECOC 26-30, pp. II-290-291 (1999).
ITU-T Recommendation G.975, 8 pages (1996).

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