Feature patterning methods and structures thereof

Details Feature patterning methods and structures thereof Feature patterning methods and structures thereof

2011-07-19

2011-07-19

Pham, Hoai v (Department: 2892)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C257SE21575, C257SE21023

Reexamination Certificate

active

07981789

ABSTRACT:
Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

REFERENCES:
patent: 7709401 (2010-05-01), Chen et al.
patent: 2007/0172770 (2007-07-01), Witters et al.
patent: 2007/0215986 (2007-09-01), Manger et al.
patent: 2008/0020329 (2008-01-01), Sugimoto
Wiaux, Vincent, et al., “Split and Design Guidelines for Double Patterning,” Optical Microlithography XXI, Proc. of SPIE, 2008, 11 pages, vol. 6924.
Hazelton, Andrew J., “Double Patterning Requirements for Optical Lithography and Prospects for Optical Extension Without Double Patterning,” Optical Microlithography XXI, Proc. of SPIE, 2008, 13 pages, vol. 6924.

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