Fault tolerant virtual VMEbus backplane design

Details Fault tolerant virtual VMEbus backplane design Fault tolerant virtual VMEbus backplane design

1999-11-18

2003-05-13

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S005110, C710S316000

Reexamination Certificate

active

06564340

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to Versa Module Eurocards (VME) backplanes and more particularly to connecting two independent VME backplanes together electrically but providing isolation in the event of a failure.
Recent shifts in the military market has driven system architectures from point-designs to commercial based technology designs. The military market has particularly focused its attention on VME-based technology for future system designs. VME backplane technology has problems in certain military applications, in particular fault tolerant designs for avionics applications. The VME backplane is very susceptible to single point failures. Currently available methods to provide fault tolerant designs using VME technology significantly degrade or compromise overall system performance.
Some of the approaches in the past are:
A device manufactured by CES, including a 10MB/s VME-to-VMEbus bridge that provides data transfer between two VME systems. The problem with this approach is one cannot directly address other system modules. Additionally, this system does not provide a direct connected system with fault-tolerant capability. Both sides must be capable of acting as independent systems as well as one virtual system.
Another is a device manufactured by General Standards including a high speed DMA card—bridge between two VME systems. This system is deficient because it cannot directly address other system modules and does not provide a direct connected system with fault-tolerant capability. Again, both sides must be capable of acting as independent systems as well as one virtual system.
Yet another system is manufactured by SBS Bit
3
called the MODEL 418 & 418-50. SBS Bit 3's Model 418 and 418-50 are high-performance repeaters for VMEbus systems. A SBS Bit 3 repeater extends a VMEbus backplane from one chassis to a second VMEbus chassis. Both chassis operate as one unit, controlled by the system controller in the primary chassis. The primary chassis can operate as a stand-alone system; it does not require the secondary chassis. The secondary chassis does not have a system controller; consequently, it cannot operate without the primary chassis. This system is unacceptable because it does not provide a direct connected system with fault-tolerant capability. Again, both sides must be capable of acting as independent systems as well as one virtual system.
Finally, an available product is manufactured by VMIC. The product is called Multimaster which allows multiple VMEbus masters in all chassis software. In the transparent mode the system allows direct communication from primary chassis to secondary chassis with no software overhead (unidirectional link control with bidirectional data transfers). In the nontransparent mode, single cycle or burst access across the link is selected by software program-controlled interrupts which allow each chassis to interrupt the other chassis. The system supports up to 25-foot cables and allows expansion to multiple VMEbus systems in a star configuration. It has switch-controlled isolation for maintenance and software-controlled Isolation. It is memory protected by user-selectable access window. Any address window in one chassis can be mapped to any window in the other chassis (e.g., extended supervisory to short nonprivileged). Window sizes are jumper selected from 256 byte to 16 Mbyte (power of two sizes, i.e., 256, 512, 1 K, 2 K, etc.). The product is compliant to VMEbus Rev. C.1 and supports 8-, 16-, and 32-bit Transfers (bidirectional), supports 16-, 24-, and 32-bit addressing (bidirectional), has two boards and two cables (in a variety of cable lengths), form a VME-to-VME link with automatic detection of remote chassis power up and supports multiple links to the same chassis. The system repeats D
0
to D
31
, A
1
to A
23
, LWORD*, AS*, DS
0
*, DS
1
*, AM
0
to AM
5
, DTACK*, and BERR*. The problems with this device are it does not provide a direct connected system with fault-tolerant capability and both sides are not capable of acting as independent systems as well as one virtual system.
Therefore, bridge designs that couple two independent VME systems together currently exist in the VME art. None of the current designs available, however, provide a virtual VMEbus design. Instead, both systems are treated as independent systems with a common data area for passing information between systems. The present invention with an integrated virtual VMEbus bridge operates as one VMEbus backplane.
SUMMARY OF THE INVENTION
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
A preferred fault tolerant virtual VMEbus backplane for computer systems comprise at least two VMEbus backplanes, each VMEbus backplane comprising a power supply and a fault detection apparatus and at least two bridge modules, each bridge module comprising a switch for connecting and disconnecting each of the VMEbus backplanes. A preferred at least two VMEbus backplanes comprise a monolithic structure. A preferred fault detection apparatus comprises a fail discrete in each bridge module. The fault detection apparatus can also comprise fail discretes in preselected modules connected to each VMEbus backplane. The fault detection apparatus preferably comprises a fault detection apparatus in each VMEbus backplane and a transmitter for transmitting the fault signal to a next VMEbus backplane. The faults comprise module fail discretes and VMEbus backplane communication tests. The preferred VMEbus backplane communication tests comprise a data transfer bus test, an arbitration bus test, and a priority interrupt bus test. The bridge modules preferably comprise a structure to connect the VMEbus backplanes to appear as a single VMEbus backplane. The structure to connect the VMEbus backplanes to appear as a single VMEbus backplane comprises direct connections between the at least two VMEbus backplanes. The preferred apparatus further comprises structure to minimize data transmission latency delays between the at least two VMEbus backplanes. The preferred structure to minimize data transmission latency delays between the at least two VMEbus backplanes comprises a direct connection between the at least two VMEbus backplanes.
The preferred method of interconnecting and disconnecting at least two computer systems, a first computer system comprising a first VMEbus backplane and a next computer system comprising a next VMEbus backplane comprises the steps of detecting a fault status in the first and the next computer system, transmitting the fault status to the other computer system, connecting the first VMEbus backplane to the next VMEbus backplane if no faults are detected, disconnecting the first VMEbus backplane from the next VMEbus backplane if a fault is detected, operating in primary mode if the fault is detected in the next VMEbus backplane, and operating in fail safe mode if the fault is detected in the first VMEbus backplane. The steps of transmitting fault status to the other computer system and connecting the first VMEbus backplane to the next VMEbus backplane if no faults are detected comprise setting fail discretes to be detected by the other computer system before connecting the first VMBbus backplane to the next VMEbus backplane. The method further comprises the step of minimizing data transmission latency delays between the first computer system and the next computer system.
The method of interconnecting a first VMEbus backplane and a second VMEbus backplane in a computer system wherein the first VMEbus backplane is connected to a primary bridge and the second VMEbus backplane is connected to a secondary bridge comprises the steps of testing the first VMEbus backplane and the second VMEbus backplane for faults, transmitting a fault/ready signal from the primary bridge

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