Fault tolerant serial arbitration system

Details Fault tolerant serial arbitration system Fault tolerant serial arbitration system

1997-07-31

2000-05-02

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 40, 710240, 710244, G06F 1320

Patent

active

060584491

ABSTRACT:
A serial arbitration system utilizes an arbitration token containing a start bit, a request bit, a set of priority bits, and an error detection bit. The arbitration token is sent to each of the other processors (20, 21, 22) and is used to arbitrate control of a shared bus (38). A processor indicates that it is the master (20) by setting the start bit (120). It enters an arbitration by setting the request bit (124). The set of priority bits (134) contains a binary priority value encoded in bit major order. This format allows an optimized parallel comparison (128, 130) of the priority values for each of the requesting processors a bit at a time. Finally, processors drop out of the arbitration upon detecting (136) a parity error in an arbitration token received from another processor.

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