Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-04-17
2001-03-13
Wiley, David A (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06202115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communications systems and methods, and more particularly, to bus bridge systems and methods.
2. Statement of the Problem
High-bandwidth busses are typically used to communicate between hosts and peripherals in applications such as computer networks. The bus interfaces used by hosts and peripherals often take different forms depending on the performance characteristics desired. For example, host devices may communicate via a differential or single-ended Small Computer System Interface (SCSI) or a Fibre Channel (FC) interface, while a peripheral such as a disk array may utilize a SCSI or other bus interface. When hosts and peripherals use disparate bus architectures, bus bridges are often utilized to provide connectivity.
Bus bridges may also be used to increase the capacity of bus systems. Bus specifications often limit, among other things, the length of the bus and the number of devices that may be attached to the bus in order to maintain performance. For example, the Peripheral Component Interconnect (PCI) bus specification commonly employed in personal computer bus applications has detailed rules for round trip propagation delay and capacitive loading which help maintain the integrity of communications at specified bus clock rates. In order to increase the capacity of such a bus, an expanded multi-layer bus structure may be used that includes a plurality of busses connected by high-speed bus bridges. This multi-layer structure can allow an increased number of devices to be interconnected while maintaining bus performance.
Complex computer systems and networks may employ multiple hosts connected to peripherals such as mass storage devices. These devices often are connected to the hosts by multiple busses and bus bridges. Consequently, data stored on these mass storage systems may be temporarily inaccessible due to a bus bridge failure, an event that can incur significant down time costs. In addition, systems that utilize bridges with storage elements, such as caches used in for Redundant Array of Independent Disk (RAID) systems that implement data striping or mirroring across multiple disks or other storage media, may be subject to data loss or corruption if the coherence of the cache is lost due to a bridge failure. Accordingly, it is desirable to increase the reliability of bus bridges to help reduce the likelihood of information loss.
Conventional techniques for improving bus bridge reliability include using bus bridge systems with redundant bus bridges between busses. In one type of conventional system, a host monitors a bus bridge to determine its health by using messages communicated over the data path connecting the host and the bridge. If the host receives a message indicating failure of the bridge, the host may route information originally intended for the failed bridge through a redundant bridge, providing what is often referred to as host-managed “failover” operation.
Host-managed failover can have many disadvantages, however. Host-managed systems tend to be operating system dependent. The reliability of a host-manage failover approach may also be compromised by relatively high failure rate elements, such as the host and data paths used to monitor and control the bus bridges, the failure of which can cause a complete failure of the data path through the bus bridge system. Maintaining cache coherency in host-managed systems may also undermine performance, as caching at the host level may require a high-bandwidth communications channel between hosts. Maintaining a host-based failover capability in the presence of potential host power supply failures may also be expensive, as an entire host computer may have to be maintained through a power outage event. Accordingly, there is a need for bus bridge systems and methods that can provide improved performance, reliability and data protection.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the present invention to provide bus bridge systems and methods that can provide increased reliability and data protection.
It is another object of the present invention to provide redundant bus bridge systems and methods that do not require host intervention.
It is another object of the present invention to provide bus bridge systems and methods that are compatible with a variety of bus architectures.
It is yet another object of the present invention to provide bus bridge systems and methods that are less operating system dependent.
According to the present invention, these and other objects, features and advantages are provided by bus bridge systems and methods in which first and second bus bridges are operative to communicate between a first bus and a second bus via respective first and second caches and to transfer information from the first bus bridge to the second cache over a third bus, e.g., a synchronous data link between the caches, to allow recovery of data previously cached in the first cache via the second bus bridge. For example, the first and second bus bridges may comprise respective first and second RAID controllers which are operative to communicate information from a host device connected to the first bus to a mass storage element connected to the second bus in a manner appropriate to implement one or more RAID levels. The second bus bridge preferably is operative to transfer information addressed to the first bus from the first bus to the second bus, e.g., to “alias” addresses normally assigned to the first bus bridge in event of a failure, disconnection or other change in status of the first bus bridge. The status may be communicated from the first bus bridge to the second bus bridge over a fourth bus connecting the first and second bus bridges. In this manner, an active/active failover capability may be provided and cached information preserved without requiring host intervention.
In one embodiment according to the present invention, the first and second bus bridges are included in respective first and second circuit assemblies that are connected to the first and second busses and to one another by a conductor assembly, e.g., a relatively high-reliability passive backplane. A respective one of the first and second circuit assemblies may be configured to be disconnected from or connected to the conductor assembly while the other of the first and second circuit assemblies maintains communication between the first bus and the second bus. Separate power supplies may be connected to each circuit assembly via the conductor assembly, and each circuit assembly may include a battery that is operative to power the bridge circuit therein responsive to a power supply failure. A redundant bus bridge system is thereby provided that can maintain communications between busses in the event of a failure of one of the bus bridges or one of the power supplies.
In another embodiment according to the present invention, the first and second caches comprise respective first and second SDRAMs. The first and second circuit assemblies comprise respective first and second clock generators that produce respective first and second clock signals. The first and second circuit assemblies are operative to synchronously transfer information from the first bus bridge to the second synchronous dynamic random access memories (SDRAMS) according to a selected one of the first and second clock signals. The conductor assembly may be configured to provide the first clock signal to the second circuit assembly, and the second circuit assembly may include a clock control circuit, responsive to the first clock signal and operative to determine a status of the first clock signal. A clock synchronizing circuit is responsive to the clock control circuit and operative to produce a clock signal synchronized to a selected one of the first and second clock signals based on the determined status of the first clock signal. Data is transferred to the second SDRAM according to the synchronized clock signal.
In yet another embodiment according to the present
Adaptec, Inc.
Duft, Graziano & Forest, P.C.
Wiley David A
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