Fault tolerant parity generation

Details Fault tolerant parity generation Fault tolerant parity generation

1999-05-20

2003-01-07

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S052000, C714S802000

Reexamination Certificate

active

06505321

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to fault tolerant parity generation.
As is known in the art, data is typically transferred from a source to a destination, or target, through a data driver and a data receiver. More particularly, referring to
FIG. 1
, a parallel bus data transmission system is shown to include a data source which produces a sequence of N bit digital data to be transmitted to a data target. Here, the data from the data source is transmitted over a backplane. The data produced by the data source is fed first to a data driver. The driver is used to provide sufficient power to drive the backplane. The data on the backplane is then fed to a data receiver. The data receiver is a high input impedance device, or buffer, used to isolate the data target from the backplane (i.e., to reduce loading on the backplane).
In order to provide some assurance of data transfer between the data source and the data target, the N bit data produced by the data source has appended to it an additional bit, i.e., a parity bit, as shown in FIG.
2
. The parity bit is representative of the number of logic 1 states in the N bit digital word. For example, if there are an odd number of logic 1 bits in the N bit word, a logic 0 parity bit may be appended to the word. In such case, the parity sense of the appended word is sometimes referred to as odd parity. In other cases, if there are an odd number of logic 1 bits in the N bit word, a logic 1 parity bit may be appended to the word. In such case, the parity sense of the appended word is referred to as even parity. In either case, the N plus one bit word is checked for parity sense by a parity checker at the output of the data receiver. A byte 00100101 protected with even parity has a logic 1 parity bit. The byte 00100101 protected with odd parity has a logic 0 parity bit. Thus, parallel data transmission with parity protection over the data is provided, given the parity bit correctly corresponds with the given protection sense, odd or even.
Typically, the data on the backplane shown in
FIGS. 1 and 2
is segmented into groups, typically bytes, where a byte is eight bits. Thus, for example, with a 72 bit backplane bus, there are 9 bytes. Furthermore, the parity scheme of
FIG. 2
is typically byte-parity, where one parity bit is generated for each byte of data. Thus, with the 72 bit backplane bus, there are 8 bytes of data and 8 parity bits.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and system are provided for providing parity protection to data. The method and system include transmitting data as a pair of groups of bits, one of the pair having odd parity and the other one of the pair having even parity. Embodiments of this method and system include transmitting the groups of bits in parallel and/or sequentially.
In accordance with another aspect of the invention a method and system are provided for providing parity protection to data. The method and system includes transmitting data as a pair of sequential transmitted groups of bits, one of the pair having odd parity and the other one of the pair having even parity.
In accordance with another aspect of the invention, a method and system are provided for providing parity protection to data. The method and system transmit a pair of groups of bits. Each one of the groups of bits has bits representing the data and a parity bit. The parity sense of one of the pair of groups of bits is opposite to the parity sense of the other one of the pair of groups of bits. The transmitted pair of groups of bits is received and their parity is checked to determine whether the parity sense of one of the received pair of groups of bits is opposite to the parity sense of the other one of the received pair of groups of bits.
With such an arrangement, a failure in the data driver or data receiver, which causes the output of all bits produced by such driver, or receiver, to assume the same logic state, can be detected because the received pair of groups of bits will have, with such failure, the same parity sense rather than the opposite parity sense as such groups of bits were transmitted.
In accordance with another feature of the invention, a method and system are provided for providing parity protection to data. The method and system includes transmitting successive groups of bits in response to clock pulses. Each one of the groups of bits has bits representative of the data and a parity bit. The parity sense of the groups of bits alternates as such groups are successively transmitted. The transmitted groups of bits are successively received in response to the clock pulses. The successively received groups are parity checked to determine whether the parity sense of the successively received groups of bits alternate with the clock pulses.
With such an arrangement, a method and system are provided for detecting a failure in the clock pulses because such a failure will result in the absence of an alternating parity sense in the successively received groups of bits.


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