Fault-tolerant multiple processor system with signature voting

Details Fault-tolerant multiple processor system with signature voting Fault-tolerant multiple processor system with signature voting

1994-08-25

2000-10-03

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

395575, 714751, G01R 3128

Patent

active

061287555

ABSTRACT:
A multiprocessor computer system and associated method having processing error detection capability is disclosed for error-free processing of an instruction set. The instruction set is replicated and processed substantially in parallel through a plurality of processing nodes of the computer system. Each processing node collects a compressed hardware signature commensurate with and derived from the execution of the instruction set. Subsequent instruction set processing, the collected hardware signatures from each processing node are compared and the presence or absence of a processing error is determined with reference to a predetermined voting scheme. Processing of the instruction sets through the plurality of processing nodes is typically asynchronous with synchronization occurring subsequent each processor's execution of the instruction set, such that each processor can be driven by an independent clock.

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