Fault tolerant memory system

Details Fault tolerant memory system Fault tolerant memory system

1997-10-24

2000-03-21

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

712 17, G06F 1120

Patent

active

060414227

ABSTRACT:
A fault tolerant semiconductor memory system has a main memory (1) having a first plurality of individually addressable storage locations. The system additionally has means for storing the address of ones of the storage locations which are defective, substitute memory comprising a second plurality of individually addressable storage locations mapped to corresponding ones of the defective storage locations, and control means comprising a plurality of comparators (20, 21, 23) for comparing a received address signal with a respective one of the addresses of the defective storage locations, each comparator being directly coupled to a corresponding one of the substitute storage locations, wherein read and write access can be re-routed from a defective storage location to the corresponding substitute storage locations.

REFERENCES:
patent: 3222653 (1965-12-01), Rice
patent: 3311887 (1967-03-01), Muroga
patent: 3331058 (1967-07-01), Perkins, Jr.
patent: 3422402 (1969-01-01), Sakalay
patent: 3434116 (1969-03-01), Anacker
patent: 3633175 (1972-01-01), Harper
patent: 3735368 (1973-05-01), Beausoleil
patent: 3753244 (1973-08-01), Sumilas et al.
patent: 4015126 (1977-03-01), Herrington
patent: 4250570 (1981-02-01), Tsang et al.
patent: 4422161 (1983-12-01), Kressel et al.
patent: 4426688 (1984-01-01), Moxley
patent: 4450559 (1984-05-01), Bond et al.
patent: 4523313 (1985-06-01), Nibby, Jr. et al.
patent: 4527251 (1985-07-01), Nibby, Jr. et al.
patent: 4532611 (1985-07-01), Countryman, Jr.
patent: 4556975 (1985-12-01), Smith et al.
patent: 4584681 (1986-04-01), Singh et al.
patent: 4639897 (1987-01-01), Wacyk
patent: 4656609 (1987-04-01), Higuchi et al.
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4744060 (1988-05-01), Okajima
patent: 4745582 (1988-05-01), Fukushi et al.
patent: 4783781 (1988-11-01), Awaya
patent: 4796233 (1989-01-01), Awaya et al.
patent: 4817056 (1989-03-01), Furutani et al.
patent: 4849938 (1989-07-01), Furutani et al.
patent: 4849939 (1989-07-01), Muranaka et al.
patent: 4862416 (1989-08-01), Takeuchi
patent: 5195057 (1993-03-01), Kasa et al.
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5243570 (1993-09-01), Saruwatari
patent: 5249156 (1993-09-01), Hagiwara et al.
patent: 5297088 (1994-03-01), Yamaguchi
patent: 5315551 (1994-05-01), Hirayama
patent: 5329473 (1994-07-01), Cangiane
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5416740 (1995-05-01), Fujita et al.
patent: 5822779 (1998-10-01), Intrater et al.
Mitchell, Jr., M.J., "Alternate Storage Position Mechanism", IBM Technical Disclosure Bulletin, vol. 12, No. 9, pp. 1478-1479, Feb. 1970.
Aichelmann, Jr., F.J., "Fault-Tolerant Design Techniques for Semiconductor Memory Applications", IBM J. Res. Develop., vol. 28, No. 2, pp. 177-183, Mar. 1984.
Morris M. Mano, Digital Design, 1991, p. 247, 429-431.

Affiliated with

Also associated with

Rating

Fault tolerant memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fault tolerant memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault tolerant memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-738966