Fault-tolerant memory array

Details Fault-tolerant memory array Fault-tolerant memory array

1983-10-28

1988-08-30

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365230, 365189, 365184, G11C 1140, G11C 800, G11C 2900

Patent

active

047681691

ABSTRACT:
A memory array is organized into rows and columns of memory cells, each cell having a configuration which passes current or blocks current depending upon the state of that cell. The array includes sense circuits to sense cell state. In a preferred embodiment of the invention, an address signal sent to the memory array activates two sets of memory cells connected to the same sense lines, and the threshold level of the sense circuits is set above the level which would be sensed for a failed bit, so that a failed bit appears as if unprogrammed or erased. Because each bit is represented by a pair of memory cells, a failed cell in a pair will not affect operation of the functioning cell in the pair or result in error.

REFERENCES:
patent: 4342103 (1982-07-01), Higuchi et al.
patent: 4422161 (1983-12-01), Kressel et al.
patent: 4471482 (1984-09-01), Young
patent: 4481609 (1984-11-01), Higuchi et al.
patent: 4485459 (1984-11-01), Venkateswaran

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