Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1999-06-11
2000-10-31
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714797, H02H 305, H03K 19003
Patent
active
06141770&
ABSTRACT:
A computer system uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer includes four or more commercial processing units (CPUs) operating in strict "lock-step" and whose outputs (33, 37) to system memory and system bus are voted by a gate array which may be implemented in a custom integrated circuit. A custom memory controller interfaces to the system memory and system bus. The data and address (35, 37) at each write to and read from memory within the computer are voted at each CPU clock cycle. A vote status and control circuit "reads" the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals are used by the agreeing CPUs 32 to continue processing operations without interruption. The system logic selects the best chance of recovering from a detected fault by re-synchronizing all CPUs, powering down a faulty CPU or switching to a spare computer, resetting and re-booting the substituted CPUs.
REFERENCES:
patent: 4751639 (1988-06-01), Corcoran et al.
patent: 5799022 (1998-08-01), Williams
patent: 5903717 (1999-05-01), Wardrop
patent: 5923830 (1999-07-01), Fuchs et al.
Fuchs Stephen
Wardrop Andrew J.
General Dynamics Information Systems, Inc.
Le Dieu-Minh T.
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