Fault tolerant computer and transaction synchronization...

Details Fault tolerant computer and transaction synchronization... Fault tolerant computer and transaction synchronization...

2007-02-13

2007-02-13

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S011000

Reexamination Certificate

active

10650667

ABSTRACT:
A fault tolerant computer includes a plurality of CPU modules that process the same instruction string while maintaining clock synchronization; and a plurality of I/O modules each having a plurality of device controllers executing input/output control processing for a device. A transaction synchronization controller, which checks if the sequences of I/O transactions issued from the plurality of CPU modules match, is provided in each device controller. If the sequences of I/O transactions issued from the plurality of CPU modules to each device controller match, a judgment is made that an out-of-synchronization condition is not caused.

REFERENCES:
patent: 5226152 (1993-07-01), Klug et al.
patent: 5398331 (1995-03-01), Huang et al.
patent: 6691225 (2004-02-01), Suffin
patent: 11-338832 (1999-12-01), None

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