Fault tolerant computer

Details Fault tolerant computer Fault tolerant computer

2008-01-08

2008-01-08

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S021000

Reexamination Certificate

active

07318169

ABSTRACT:
A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).

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Mukherjee et al.; “Detailed Design and Evaluation of Redundant Multithreading Alternatives”; International Conference on Computer Architecture, Proceedings of the 29thAnnual International Symposium on Computer Architecture; published 2002; pp. 99-110.
Reinhardt et al.; “Transient Fault Detection Via Simultaneous Multithreading”; International conference on Computer Architecture, Proceedings of the 27th Annual International Symposium on Computer Architecture; published 2000; pp. 25-36.

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