Fault tolerant clock voter with recovery

Details Fault tolerant clock voter with recovery Fault tolerant clock voter with recovery

1998-11-20

2001-08-07

Heckler, Thomas M. (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C714S814000

Reexamination Certificate

active

06272647

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to fault tolerant clocks and more particularly to a novel clock voter having the ability to recover from temporary faults.
DESCRIPTION OF THE PRIOR ART
U.S. Pat. No. 5,404,363 of James M. Krause et al entitled “Two Fail-Operational Fault-Tolerant Multiple Clock System” and assigned to the assignee of the present invention is incorporated herein by reference. The '363 patent describes a fault tolerant clock which requires initial synchronization of up to four clock signals and which includes a circuit that operates to produce a fault signal whenever a clock signal has a leading edge that occurs too early or too late with respect to a reference clock or has a trailing edge that occurs too early with respect to the reference clock or which has excessive noise. These signals are described in connection with FIG. 9 of the '363 patent.
In operation, if any of the faults occur, a fault signal is sent to a latch therein (a D flip-flop 96 in the '363 patent) and a fault output occurs which prevents the faulty clock signal from being used in the voter.
An undesirable feature arises in the operation of the circuit of the '363 patent when a fault is corrected. With the above described operation, the D flip-flop which was set by the occurrence of a fault cannot be reset until a “clock enable” signal occurs which is basically only at the start of operation. Thus, even though a clock signal may no longer be faulty, it cannot be used by the voter. While some systems are shut down relatively frequently (e.g. daily) so that system reset signals occur not too infrequently, some applications, such as Digital Global Positioning Systems (DGPS), are in operation for many months and system reset signals are too infrequent for practical use.
The circuit of the '363 patent also requires synchronous start up of the clocks which is acceptable when all circuits can be started in a controlled time interval of each other. However, in some desirable uses of a fault tolerant clock, such as DGPS, signals from multiple satellite receivers are used. The receivers are independent from each other and when they acquire sufficient satellite signals they begin to output time mark signals. Although the satellite receivers may be energized simultaneously, each receiver will not complete acquisition at the same time so the time marks do not start simultaneously. This asynchronous start up would cause the circuit of the '363 patent to fault the inputs and to fail to issue a voted time signal.
SUMMARY OF THE INVENTION
The present invention solves these and other needs by providing a modified fault response circuit. Since no single reset pulse is appropriate for all of the fault types, a separate latch for each of the possible faults to be detected is incorporated. Each latch has its own reset which is performed regularly, often and independently of the clock enable signal so that when a fault is corrected and becomes valid again, the clock signal can quickly be used to contribute to the voted output. Furthermore, with each fault having its own latch, asynchronous start up is possible since any latch set at start up would be reset shortly after reception of a valid signal.


REFERENCES:
patent: 4542509 (1985-09-01), Buchanan et al.
patent: 4800564 (1989-01-01), DeFazio et al.
patent: 4811343 (1989-03-01), Johansson et al.
patent: 5377206 (1994-12-01), Smith
patent: 5404363 (1995-04-01), Kraus et al.
patent: 5537583 (1996-07-01), Truons

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