Fault-tolerant clock generator

Details Fault-tolerant clock generator Fault-tolerant clock generator

2006-07-10

2008-12-16

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C714S002000

Reexamination Certificate

active

07467320

ABSTRACT:
A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.

REFERENCES:
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patent: 5557623 (1996-09-01), Discoll
patent: 5742798 (1998-04-01), Goldrian
patent: 5852728 (1998-12-01), Matsuda et al.
patent: 6194969 (2001-02-01), Doblar
patent: 6731709 (2004-05-01), Doblar
patent: 2000035831 (2000-02-01), None

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